Abstract: A digital demodulator that may be utilized in integrated radio receivers and/or integrated radios includes a mixing section, 1st and 2nd digital comb filters, phase locked loop module, and a data recovery module. The mixing section is operably coupled to produce a digital I signal and a digital Q signal from a digital intermediate frequency signal. The 1st comb filter filters the digital I signal while the 2nd comb filter filters the digital Q signal. The phase locked loop module produces a digital signal from the filtered I and filtered Q signals. The data recovery module interprets the digital signal to recapture a data stream.

Abstract: The present invention relates to a system and method for selecting one of plurality of PRBS generators for use with a modem. The modem includes a measuring device adapted to measure an operating environment of the modem; and a storage device adapted to store a list of PRBS generator definitions. The modem selects one of a plurality of PRBS generators based on the measurement of the operating environment.

Abstract: A magnitude comparator circuit may include a first circuit coupled to receive the operands to be compared, a second circuit coupled to the first circuit, and a third circuit coupled to the second circuit and coupled to receive a first operand of the operands to be compared. The first circuit is configured to generate a vector indicative of whether or not bits in the first operand and the second operand are equal. The second circuit receives the vector, and generates an indication of the first bit, beginning with the most significant bit, at which the first operand and the second operand differ. The third circuit receives the indication, and generates an indication of whether or not the first operand is greater than the second operand. In one embodiment, the first, second, and third circuits are included in a combined magnitude compare/count leading zero circuit.

Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.

Abstract: The present invention relates to a programmable memory device and a method of setting a state for a programmable memory device. In at least one embodiment, the memory device comprises at least a level shifter adapted to stand off a high programing voltage to at least one fuse element in the memory device, wherein the high programming voltage is used to set a state of the memory device.

Abstract: An output buffer includes first and second circuit portions coupled between input and output terminals. Each circuit portion includes a capacitive element; an output transistor having a gate coupled to the capacitive element, and a drain that drives a voltage at the output terminal; and a current generator configured to generate a charging current that is directed to the capacitive element responsive to a logic transition at the input terminal, wherein the charging current causes a substantially linear ramp voltage to form at the gate of the output transistor, whereby the ramp voltage controls a slew rate of the output terminal voltage.

Abstract: A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed includes the steps of varying a spectral allocation and constellation size with which communication is performed, so as to define a combination of spectral allocation and constellation size at which the bit rate and/or margin are enhanced. The spectral allocation can be varied by varying a stop frequency thereof, while maintaining a substantially constant start frequency, so as to mitigate undesirable high frequency content of the bandwidth. Alternatively, both start and stop frequencies may be varied.

Abstract: A method and apparatus for coupling a voiceband modem circuit to a common phoneline connector, the common phoneline connection having a ring line connection and a tip line connection which couples a ring/tip line pair to a subscriber loop circuit, the voiceband modem circuit operating in a voiceband modem operating frequency band and having a voiceband modem interface ring line and a voiceband modem interface tip line. The voiceband modem interface ring line is coupled to the ring line and the voiceband modem interface tip line is coupled to the tip line connection by inserting, between the ring line connection and the voiceband modem interface ring line and between the tip line connection and the voiceband modem interface tip line, a series pair of inductors. A first inductor of the series pair has a low inductance and a high self-resonant frequency and a second inductor of the series pair has a high inductance and low self-resonant frequency.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: The present invention relates to storage element. At least one read port is coupled to the storage element and a sensing device is coupled to the read port, where the read port is coupled to the storage element in an isolated manner. The sensing device is adapted to sense a small voltage swing. The sensing device includes two inverters comprising input offset and gain stages.

Abstract: A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point (35) and a second bit of complementary data at a second point (36). A first transistor (40) comprising a first gate (42) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (14 and 16). Second and third transistors (50, 60) comprise gates (52, 62) coupled to the first line (14) and second line (16) and comprise circuit paths (54, 56, 64, 66) coupling the first and second points to the first gate.

Abstract: A multiple layer inductor has a first spiral conductive pattern disposed on a first surface; a second spiral conductive pattern disposed on a second surface; a continuing interconnection coupled to the first and second spiral conductive patterns; an interface coupled to the first and second spiral conductive patterns; and a conductive shield pattern disposed on a third surface that is adjacent to the second surface. The interface includes a first terminal disposed on the first surface that is coupled to the first spiral conductive pattern. The interface also includes a second terminal that is disposed on the first surface and coupled to said second spiral conductive pattern.

Abstract: A system reduces unwanted oscillations in a multiple gigabit per second, high gain amplifier portion. The system includes a power source portion having a plurality of power sources and a bias current portion having a plurality of bias current devices. The system also includes an amplification portion having a plurality of amplifiers. A first group of the plurality of amplifiers is coupled to the power source portion and the bias current portion, such that feedback voltage is substantially eliminated to substantially eliminate oscillations in the amplification portion.

Abstract: A system and method is provided for supplying power over a home phone line network in a manner that is interoperable with other voice and data services operating on the same network. The system includes a power source coupled to the home phone line network. The power source includes an AC signal generator that generates an AC signal at a selected frequency. The power source also includes a band pass filter for removing unwanted harmonics from the AC signal, thereby generating a filtered AC signal for powering one or more devices on the home phone line network. One or more devices attached to the home phone line network, such as a telephone adapter or telephone, receives the filtered AC signal. Each device comprises a second band pass filter and an AC/DC converter. The second band pass filter passes the filtered AC signal to the AC/DC converter and prevents the introduction of undesired harmonics onto the home phone line network from the AC/DC converter.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: Methods and apparatus for testing wireless devices. Devices being tested receive and transmit radio frequency test signals. These radio frequency test signals are received or transmitted using an antenna associated with the device, and then are transmitted or received using a unique wide-band tapered-slot antenna connected to a test system. The wide-band tapered-slot antenna has an input path that is substantially orthogonal to the tapered slot, and one of the conductors defining the slot is grounded.

Abstract: A balancing/unbalancing (balun) structure for operating at frequency f1 includes a microstrip printed circuit board (PCB). A balun on the PCB includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter on the PCB is wrapped around the balun and includes a first folded element with a transmission length of ?2/4 and connected to the output port. A second folded element has a transmission length of ?2/4 and connected to the tap point. A third folded element connects the tap point to the output port and has a transmission length of ?2/4.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: The present invention relates to a high voltage switch used with a one-time programmable memory device and a method of setting a state of a one-time programmable memory device using such a high voltage switch. The memory device includes a plurality of one time programmable memory cells arranged in an array and adapted to be programmed using a high voltage, wherein each of the memory cells includes at least one storage element and two gated fuses connected to the storage element. A high voltage switch is connected to at least one of the memory cells and is adapted to switch in a high voltage.