Abstract: A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. The partial products are accumulated to generate a product (P). To compensate for the quantization error, Booth encoder outputs are used for the generation of error compensation bias. The truncated bits are divided into two groups, a major least significant bit group and a minor least significant bit group, depending upon their effects on the quantization error. Different error compensation methods are applied to each group.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract: A data communications device includes a base unit having a first microprocessor and a data and communication module received by the base unit that includes a second microprocessor and a transceiver. The data and communication module is selected from a plurality of data and communication modules each having different types of transceivers. A program is stored in one of the base unit and the data and communication module to control communication of control signals and data between the first microprocessor and the second microprocessor according to a uniform data protocol that is understandable to the base unit.

Abstract: An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and second memory sections. During a read operation, the buffer can receive a first portion of a misaligned data word from the first memory section and read a second portion of the misaligned data word from the second memory section and assemble the data in the data word from the first and second portions. When the access operation is a write operation, the buffer can effectively perform a shift operation on the data in the data word, then write a first portion of the word to the first memory section and write a second portion of the word to the second memory section. Accordingly, data accesses that would take two memory-access cycles on a conventional memory system are reduced to a single memory-access cycle.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract: A network gateway is configured to facilitate on line and off line bi-directional communication between a number of near end data and telephony devices with far end data termination devices via a hybrid fiber coaxial network and a cable modem termination system. The described network gateway combines a QAM receiver, a transmitter, a DOCSIS MAC, a CPU, a voice and audio processor, an Ethernet MAC, and a USB controller to provide high performance and robust operation. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

Abstract: Provided is a method and system for producing a drive signal for a current steering amplifier. An exemplary method comprises receiving a supply voltage signal and a differential input signal as a circuit input. A differential amplifier drive signal is produced in response to the received supply voltage signal, the received differential input signal, and the received differential control signal. The received differential input signal is adjusted to a value where magnitudes of negative and positive components of the differential control signal become equal to one another and are within a predetermined amount of a magnitude of the supply voltage signal.

Abstract: A method and system for processing a data flow in a multi-channel, multi-service environment is described. In one embodiment, a socket is dynamically allocated, the socket including a dynamically allocated service. Further, the server processes the data flow based upon the type of data being processed.

Abstract: The disclosure relates to providing a secondary communication channel overlaid on a primary communication channel, using an enhanced encoding method, to effectively expand the utilized information capacity of the primary communication channel. A portion of at least a first word of one or more packets may be encoded in a datastream. A running disparity of the encoded word may be reversed. Hence, if an encoded running disparity of an encoded word is RD positive RD(+), then the running disparity is reversed to RD negative RD(?). Similarly, if an encoded running disparity is RD negative RD(?), then the running disparity is reversed to RD positive RD(+). The word may be a data word, control word or an idle word corresponding to a data packet, a control packet and an idle packet, respectively.

Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.

Abstract: A voltage regulator includes a first stage capable having a first current flowing through it. A second stage has a second current. A third stage is capable of outputting an output voltage and has a third current flowing through it. The first, second and third currents are proportional to each other throughout a range of operation of the voltage regulator between substantially zero output current and maximum output current. The first stage drives the second stage as a low input impedance load.

Abstract: Downstream synchronous multichannel (DSSM) communications are provided among a plurality of carriers, each being a completely DOCSIS™ 2.0-compliant downstream. The synchronous multichannels support communications with both DSSM-capable communications nodes and non-DSSM-capable communications nodes (e.g., legacy cable modems). Non-DSSM packets are transmitted on a single channel. DSSM packets are split into multiple pieces, which are transmitted simultaneously on all available channels. Since the physical delay variation (e.g., group delay change) across the adjacent carriers is small (on the order of a symbol time), the multiple pieces arrive at the receiving communications nodes at nearly the same time and can be reassembled with minimal buffering and no packet ordering problems. To avoid causing trouble for the non-DSSM-capable communications nodes, the packet pieces are encapsulated with a header that causes the non-DSSM-capable communications nodes to silently discard them.

Abstract: A communications management system introduces a low bandwidth phase locked loop (LoBW-PLL) working in tandem with a high bandwidth phase locked loop (HiBW-PLL). The LoBW-PLL only needs to follow the average frequency of the transported clock and not all of the excursions made by the master clock. During periods of downstream outage, the LoBW-PLL opens its loop and free wheels such that disturbances caused by a reacquisition do not impact the concept of time for the LoBW-PLL. After reacquisition, the LoBW-PLL and HiBW-PLL are compared to determine if a timing error has occurred. If a timing error is detected, the magnitude of the timing error is measured upon completion of the reacquistion cycle, and this measurement is used to correct the timing error.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks.

Abstract: Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate and receiving a clock signal having a first clock frequency, and alternating between a first level and a second level. The data signal is stored when the clock signal alternates from the first level to the second level, and the stored data signal is provided as a first signal a first amount of time later. The first signal is stored when the clock signal alternates from the first level to the second level, and the stored first signal is provided as a second signal a second amount of time later. A third signal is provided by delaying the first signal for a third amount of time. The third signal is stored when the clock signal alternates from the second level to the first level, and the stored third signal is provided as a fourth signal a fourth amount of time later. A fifth signal is provided by delaying the data signal a fifth amount of time.

Abstract: A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to store bits of data at first and second points (35 and 36). A first transistor (26) is coupled to the word line, the first bit line and the first point. A second transistor (27) is coupled to the word line, the second bit line and the second point. The word line voltage is changed in accordance with process parameters to allow conduction by the first and second transistors to compensate for leakage by the pair of transistors. For example, the first and second transistors may be operated in a triode mode.

Abstract: Each packet normally consists of a preamble, start-of-frame delimiter and data. The preamble has nibbles each having a particular format. A header substituted for preamble nibbles by an individual one of the originating devices in a plurality, and an individual one of the ports in such originating device, indicates such originating device and such port. Such port in such originating device sends such modified packet to others of the originating devices and to an observing station. The header format is such that the last nibble in the header and the remaining preamble portion will not be confused with any two (2) nibbles in the header. A particular one of the originating devices indicated in the data converts the header back to the preamble format and transmits the converted packet to a receiving station. The observing station records the individual originating device, and the individual port in such device, indicated in the header.