Abstract: A modem includes a Digital Access Arrangement (DAA) Circuit and modem software that is executed by a processor. When the DAA Circuit detects that the modem software is nonfunctional, it enters an on-hook state to prevent blocking of a coupled telephone line. A nonfunctional state of the modem software is detected when the modem software ceases to interact with the DAA Circuit in an expected manner. In a first operation, the nonfunctional state is determined when the modem software does not reset a count down timer in the DAA Circuit before the count down timer reaches a termination value. In a second operation, the nonfunctional state is determined when the modem software does not access the DAA Circuit before the count down timer reaches the termination value. In a third operation, the nonfunctional state is determined when the modem software ceases writing transmit data to DMA memory.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A power supply multiplexing circuit including a first supply voltage input. A first pair of cascoded PMOS transistors are in series with the first supply voltage input. A first native NMOS transistor is in series with the first pair of cascoded PMOS transistors. Also, a second supply voltage input and a second pair of cascoded PMOS transistors are in series with the second supply voltage input; and a second native NMOS transistor in series with the second pair of cascoded PMOS transistors. The gates of the first and second native NMOS transistors are driven by two control signals out of phase with each other, and sources of the first and second native NMOS transistors are connected together to output an output voltage.

Abstract: A portable terminal is provided with an internal connector accessible via an opening at one end of the terminal. A peripheral device is integrated with the terminal by coupling a peripheral circuit with the connector via the opening. A peripheral housing may serve to protectively cover the opening. The connector may be coupled with a terminal processor system and with the terminal power supply.

Abstract: Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as changing the step size of the PGA. By placing the resistance of the highpass filter in parallel with a programmable attenuator divider, the steps of the PGA can be minimally affected as the highpass frequency is adjusted.

Abstract: The present invention relates to a system and method for equalizing the capacitance between at least two lines of a bus running in parallel for a portion of their length. The system and method include determining a twisting pattern for the lines using an algorithm. After determining the twisting pattern, the lines are twisted according to the pattern so that each of the lines runs along every other line for a same distance across the length of the bus.

Abstract: A system and method for the secure storage of executable code and the secure movement of such code from memory to a processor. The method includes the storage of an encrypted version of the code. The code is then decrypted and decompressed as necessary, before re-encryption in storage. The re-encrypted executable code is then written to external memory. As a cache line of executable code is required, a fetch is performed but intercepted. In the interception, the cache line is decrypted. The plain text cache line is then stored in an instruction cache associated with a processor.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: An FFT conversion instruction based on a single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform conversion processing used in an FFT computation. In an embodiment, the FFT conversion instruction implements two instances of a conversion operation, i.e., 2-way SIMD, over two sets of complex points at once. A control register or variant opcode controls an inverse flag to control the behavior of the conversion process. In an embodiment, the control register contains a control bit to select between forward and inverse FFT context.

Abstract: A method and apparatus for debugging are described. In one embodiment, a target construct is selected for debugging. Data related to an operation of the target construct is accessed by a debug construct in real time. At least a portion of this data is retrieved without disturbing the operation of the target construct to debug the target construct.

Abstract: A data communication system capable of forwarding IP-addressed data to devices as such devices move among networks having different IP addresses is disclosed herein. The system includes first and second networks containing first and second pluralities of nodes. At least one of the first plurality of nodes is adapted to receive data transmissions from an external IP-based network. Upon joining the first network, this device is assigned an IP address which remains with it irrespective of whether it moves beyond the range of the first network. When this device roams into the vicinity of the second network, data addressed to the device which is received at the first network is forwarded via at least one node of the second network to the device.

Abstract: A method and apparatus for obtaining a channel estimate and a baud frequency offset estimate for a communications channel in a communications system. The communications system has a transmitter for transmitting to a receiver over the communications channel signals representing data appended to a preamble signal. The preamble signal is provided as a periodic plurality of preamble sequences, each preamble sequence being generated in accordance with: 1 32 ? ? k = 0 15 ? ? ? b k ? b mod ? ( k + n , 16 ) * = { 1 , n = 0 0 , n ? 0 . A signal representing the periodic plurality of preamble sequences is sent by a transmitter over the communications channel to a receiver and is received at the receiver as a received signal.

Abstract: A method of determining an end of a transmitted frame at a receiver on a frame-based communications network. An end of frame format for the transmitted frame is provided having an end of frame plurality of symbols. A received transmitted frame is filtered using filter coefficients matched to the end of frame plurality of symbols to provide a correlation sequence low-pass filtered signal. A squared magnitude of the correlation sequence is computed. The squared magnitude of the correlation sequence is low-pass filtered to provide a low-pass filtered correlation signal. The low-pass filtered correlation signal is delayed to provide a delayed low-pass filtered correlation signal. The delayed low-pass filtered correlation signal is multiplied by a fixed predetermined threshold to provide a multiplied correlation signal. The multiplied correlation signal is compared with the low-pass filtered correlation signal to provide a match/no match comparison indicative of the possible end of a transmitted frame.

Abstract: A balancing/unbalancing (balun) structure includes a microstrip line printed circuit board (PCB). Two input ports are coupled to a differential signal. An isolated port is connected to ground through a resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and the output port, wherein distance between adjacent traces is approximately twice PCB thickness.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.

Abstract: A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches are closed, a second pair of back-to-back transistors is connected to the first pair so the two pairs acting together serve as a dynamic latch.

Abstract: A method, apparatus and processing instruction for performing DMT encoding substantially simultaneously on one tone or multiple tones comprises the steps of: (a) using a first input operand comprising one or more bit-group data values, each to be encoded for one or more tones; (b) using a second input operand comprising one or more bit-group size values corresponding to the bit-group data values in the first input operand; and (c) generating an output comprising a result of encoding the bit-group data value or values from the first input operand by mapping each of the bit-group data values from the first input operand onto a location in a constellation as determined by the corresponding bit-group size value or values from the second input operand.

Abstract: Methods and systems for detecting defects in serial link transceivers. Defect detection includes detecting open circuits in one or more of the transmission lines, detecting short circuits between one or more of the transmission lines and a power supply, detecting short circuits between the transmission lines, or detecting short circuits across optional AC-couplings in the transmission lines. The detection can include direct or indirect detection of voltage or current.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.