Abstract: A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory is already in use by other system functions, utilizing such unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.

Abstract: A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal.

Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has a driver portion that generates drive signals based on received respective digital input signals. The drive signals are received at respective switches in the analog section. The driver portion includes logic gates that are used to generate the drive signals, such that a rise and fall time of complementary pairs of drive signals are substantially equal. The driver portion can optionally include an acceleration system to accelerate the rise and fall times of the drive signals. The switches generate respective analog signals from the drive signals.

Abstract: Presented herein is a system and apparatus for accelerating arithmetic decoding of encoded data. In one embodiment, there is presented a symbol interpreter for decoding CABAC coded data. The symbol interpreter comprises a first memory, a CABAC decoding loop, and a syntax assembler. The first memory receives a bitstream comprising the CABAC coded data at a channel rate. The CABAC decoding loop decodes the CABAC symbols at the channel rate, and comprises an arithmetic decoder for generating binary symbols from the CABAC coded data at the channel rate. The syntax assembler decodes the binary symbols at a consumption rate.

Abstract: In a multi-carrier transmission scheme (frequency domain multiplexed—FDM), a single high rate data stream is split into multiple lower rate data streams each transmitted over a different carrier (e.g., a tone or bin). The data rate possible from a multiple-carrier transmission scheme is theoretically equivalent to the data rate possible from a single-carrier (including baseband) scheme with the same composite bandwidth. The scheme allows for a communications system that can selectively send each data signal (e.g., audio data, video data, raw data, etc.) partitioned out into full and half duplex sections (e.g., tones). The scheme can have a reduced complexity and cost and use less bandwidth. This is done by being able to selectively split a data signal into both full and half duplex tones.

Abstract: A two way communication system is adapted to reduce latency while the communications system is operating in a low power mode. The two way communication system includes a local host having a first primary communication channel and a secondary out of band transmitter; and customer premise equipment having a primary communication channel for communicating with the first primary communication channel of the local host and a secondary low power out of band receiver that receives out of band control signals from the out of band transmitter during low power operation of the customer premise equipment.

Abstract: An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase &phgr;2 and substantially rejecting the signal corresponding to the output signal during the clock phase &phgr;1.

Abstract: Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

Abstract: The present invention establishes a communications link between a central office (CO) modem and a customer premise equipment (CPE) modem. The CO modem then evaluates the performance of the communications link. Impairments on the communications link are identified based on the evaluation results. Next, adjustment parameters for improving the performance of the communications link are determined. The CPE modem is then modified in accordance with the determined adjustment parameters to establish an adjusted communications link between the CO modem and the CPE modem. In this way, impairments such as bridged taps and cross-talk can be avoided.

Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.

Abstract: An interleaving operation can scramble (permute) a data stream, or each dimension (set of symbols (a, b, c, . . . )) in a data stream, immediately following FEC encoding or dimension multiplexing of the data stream. Bursts of errors might be combined with the permuted data before, during, or after transmission. A de-interleaver reorders the received symbols and, in the process, spreads (separates) the bursts of errors. Also, using the multi-dimensional interleaving and de-interleaving can balance SNR on each channel. Spreading the errors and/or balancing SNR can keep bursts from overwhelming the FEC decoder or an FEC decoder in any one channel. In one example, interleaving and de-interleaving can be used to scramble data over Ethernet twisted wire pairs. In another example, interleaving and de-interleaving can be used to scramble data or information broadcast via wireless telecommunications channels (e.g., radio frequency channels, multi-antenna channels, etc).

Abstract: Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp.

Abstract: A process of repairing defects in linked list memories is disclosed. One of the linked list memories is selected as a defect marking memory and faults in rows of the defect marking memory are detected. Row addresses having at least one fault in defect address registers are stored; when at least one fault in the rows of the defect marking memory is detected. Faults in rows of other linked list memories are detected, where the other linked list memories are the linked list memories other than the defect marking memory and a marking code is stored for each row address of the other linked list memories in the defect marking memory, where a particular marking code indicates whether a particular row address has at least one fault. The defect address registers and the defect marking memory are searched when addresses of the linked list memories are linked and row addresses indicated as having at least one fault are skipped in the linking process.

Abstract: An input buffer amplifier has a symmetrical centroidal layout. The input buffer amplifier includes two half differential amplifiers that have substantially identical layouts. Each half amplifier receives the input signal in-parallel, and the outputs of the differential half amplifiers are wire-ored together. The input buffer amplifier is symmetrical about both horizontal and vertical lines of symmetry. Furthermore, FET devices forming the half amplifiers are interlaced to create the horizontal line of symmetry. The overall horizontal and vertical symmetry of the input buffer amplifier improves the device matching between differential signal paths. In other words, the devices in the half amplifiers that process the positive and negative components of the differential signal are more closely matched. This reduces differential offsets and common mode offsets that can occur when devices are not matched properly.

Abstract: A line driver selectively drives one of two transmission lines. The line driver includes a differential amplifier connected to first and second differential switches. The first differential switch is connected between an output of the differential amplifier and a first of two transmission lines. The second differential switch is connected to the output of the differential amplifier and to the second of two transmission lines. The first and second differential switches are controlled by respective first and second control signals. The output of the differential amplifier is connected to either the first or the second transmission line in response to the first and second control signals. The differential switches include loopback protection to an prevent an incoming signal from passing from one transmission line to another during power down mode.

Abstract: Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

Abstract: A method of processing sampled voice packets from a voice packet sender for transmission over a bit-rate sampled data transmission system, such as by a cable modem over a cable modem termination system, to a voice packet recipient. Unsolicited grant arrivals in response to a request from the voice packet sender coupled to the cable modem are determined. The storing of sampled voice packets is synchronized with the unsolicited grant arrivals. Upon receipt of an unsolicited grant arrival, currently stored sampled voice packets are transmitted to the cable modem for further transmission to the voice packet recipient over the cable modem termination system.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

Abstract: A method (and a computer accessible medium comprising one or more instructions which, when executed, implement the method) is contemplated. At least a first timing path is identified in a first timing report corresponding to a first partition of a circuit. For at least one timing constraint applied to the first timing path, a second timing path in a second partition of the circuit that causes the timing constraint is determined. A second timing report comprising the first timing path from the first timing report and the second timing path from the second partition is generated.

Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.