Abstract: A digital memory system (30) includes a memory cell (10), a bit line (12), a voltage generator (320) a controller (90) and a charge integrity estimating module (135). A series of successively larger operating voltages are transmitted to the cell from the voltage generator. The controller determines whether a predetermined value has been stored in the cell. The charge integrity estimating module detects the quantity of charge in the memory cell, for example, by using a sense amplifier (170).

Abstract: A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0?, x1?} such that a number of 1's at bit x0? over time is within ?1 of a number of 1's at bit x1?. At least two 4-bit vector shufflers input the vectors {x0?, x1?}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0?, x1?} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0?, x1?} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different signal input rates of an input signal are provided. The system includes a phase locked loop system and a parameter controller. The method includes monitoring an input signal, determining a signal input rate of the input signal, providing shift factors to a loop filter contained within the signal recovery system, and adjusting the phase locked loop system performance based on the shift factors. The performance factors that can be modified include the acquisition rate, loop bandwidth, and damping factor of the phase locked loop system within the signal recovery system.

Abstract: A transmitter unit for transmitting data via a data link is described, wherein the transmitter unit comprises a header compression unit adapted for converting a primary header of a data packet to be transmitted into a corresponding secondary header, with said primary header being related to said secondary header in one-to-one correspondence. The transmitter unit is adapted for transmitting a modified data packet via said data link, said modified data packet comprising the corresponding secondary header. Furthermore, a receiver unit for receiving data transmitted via a data link is described. The receiver unit comprises a header decompression unit adapted for converting a secondary header of a modified data packet received via said data link into a corresponding primary header.

Abstract: There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to effects of clock skew, each delay element having a physical form and at least one input terminal and at least one output terminal; determining which delay elements are not critical in preventing shoot-through; removing non-critical delay elements from the circuit; and replacing each removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element. This wire cell has the effect of removing the delay element from the circuit without having to reposition the circuit components. This has the result that it is not necessary to re-position circuit components on the removal of delay elements and then to re-evaluate the circuit performance. Circuit design can be significantly improved.

Abstract: A method of mirroring data to a mirrored to port in a plurality of switches. The method has the steps of determining if data was sent to all of said plurality of switches; determining if said data was sent to a mirrored to port (MTP); and resending said data to all of said plurality of switches if mirroring is enabled and said data was not sent to said MTP.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: Present herein is a low memory and MIPS efficient technique for decoding Huffman codes using multi-stage, multi-bits lookup at different levels. A binary tree is cut at levels depending on the quotient of the number of existing nodes and the number of possible nodes.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequence currents, including methods and systems for biasing transistors in paths susceptible to power-on sequence damage such that these paths do not have substantial current flow unless the power supplies controlling the gate of the susceptible transistors are powered on. In an embodiment, the invention is applied to a circuit having a first and second IC terminals coupled to a first and second power supplies, respectively. The invention protects the circuit in the event that the first power supply is powered-on before the second power supply is powered-on. The method includes sensing voltage amplitudes from the first and second power supplies. When first power supply is powered-on before the second power supply is powered-on, the first IC terminal is coupled to the second IC terminal. The substantially prevents undesired power-on sequence currents from flowing between the first and second IC terminals.

Abstract: Methods and systems for selecting contexts during decoding of arithmetic code are disclosed. Aspects of the method may comprise assigning a plurality of default context identifiers to a plurality of current syntax elements within a current macroblock. A plurality of adjacent context identifiers may be acquired, where the adjacent context identifiers may be associated with a plurality of syntax elements within at least one macroblock adjacent to the current macroblock. At least one of the plurality of adjacent context identifiers may be selected utilizing at least one of the default context identifiers. Each of the default context identifiers may comprises a binary value. A top-adjacent context identifier associated with a syntax element within a top-adjacent macroblock to the current macroblock may be acquired. A left-adjacent context identifier associated with a syntax element within a left-adjacent macroblock to the current macroblock may be acquired.

Abstract: The present invention relates to a transceiver for bidirectional frequency division multiplexed transmission, a communication system including one or more transceivers. Optionally, the communication system is a communication system for a digital subscriber line. The transceiver comprises transmission means with a voltage source output or a current source output for transmitting data in a transmission frequency range, receiving means for receiving data in a receiving frequency range, and a coupling impedance for connecting the transmission means and the receiving means to a transmission medium. The magnitude of the coupling impedance in the transmission frequency range is smaller than the magnitude of the coupling impedance in the receiving frequency range if the transmission means has a voltage source output and is higher than the magnitude of the coupling impedance in the receiving frequency range if the transmission means has a current source output.

Abstract: Methods, systems, and devices are provided for managing flow of datagram traffic, generally across networks. According to some of these methods, a flow control mechanism is used to avoid over-subscription of some ports without pausing extended areas of a network. According to other methods, a congestion control mechanism is used to minimize datagram traffic between a port sending datagrams to an over-subscribed port and the over-subscribed port itself.

Abstract: A method of replicating multicast datagrams in a network device is disclosed. The method includes the steps of determining by a memory management unit whether a scheduled outgoing datagram stored in a main memory is a multicast (MC) packet. When the scheduled outgoing datagram type is the MC datagram, the method also includes performing a lookup of a replicate count table to determine a copy count value and writing the copy count value to a copy count register, awaiting a ready signal from an egress port of the network switch and sending the outgoing datagram to the egress port from the main memory along with the copy count value. The method also includes changing the copy count value in the copy count register, modifying a VLAN identifier of the outgoing datagram if necessary based on the copy count value and forwarding the outgoing datagram from the egress port.

Abstract: A method of mediating the flow of datagrams to a destination in a network is disclosed. The method includes the steps of receiving a datagram at a port of a network device, evaluating a destination address for the datagram based on fields in the incoming packet, searching a longest prefix match (LPM) table using the destination address as a LPM key, determining an address table index and an offset based on entries found in the search of the longest prefix match table, searching an address table using the address table index and the offset as an address key to determine an egress port number of the network device and forwarding the packet based upon at least the egress port number.

Abstract: First and second address-selection information, as well as first and second read/write information, is contemporaneously provided to various enabling circuits. The enabling circuits can then enable one or more first memory cells based on the first address-selection and first read/write information, and further enable the one or more second memory cells based on the second address-selection information and read/write information. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.

Abstract: Data packets transmitted over a cable network are suppressed by hardware at the transmitting end and expanded on the receiving end. This conserves bandwidth as well as reduces the processing resource requirements in both the CM and the CMTS. An extended header element is added to a data packet that is to be transmitted over the cable network. The extended header element contains an index that is used along with the SID to access a rule. The rule is used to determine which bytes are to be suppressed at the transmitter and expanded at the receiver.

Abstract: A method of distributing data across a network having a plurality of equal-cost paths. Also, a device for distributing data over a network according to the method. The data, which is typically contained in data packets, may be distributed based on at least one attribute of each of the packets. The data may also be distributed according to a weighted distribution function that allows for unequal amounts of traffic to be distributed to each of the equal-cost paths.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.