Abstract: A communications component comprises a first data port interface supporting a plurality of data ports transmitting and receiving data. A second data port interface supports a plurality of data ports transmitting and receiving data. An internal memory communicates with the first data port interface and the second data port interface. A memory management unit includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A plurality of independent communication channels is provided. The independent communication channels communicate data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. The memory management unit directs data from one of the first data port interface and the second data port interface to one of the internal memory and the external memory interface according to a predetermined algorithm.

Abstract: A method and system for utilizing processor(s) and bypass processor(s) of a computer graphics system are disclosed. The processor(s) and bypass processor(s) render primitives, which are ordered based on their left corners. The method and system include providing a merge circuit, a distributor, a feedback circuit and a controller. The merge circuit determines left and right edges for each primitive. The distributor is coupled with feedback circuit and outputs a first portion of the primitives. The distributor provides a second portion of the primitives to the processor(s) and a third portion of the primitives to the bypass processor(s) if the first portion includes more primitives than there are processor(s). The second portion includes no more primitives than there are processor(s). The feedback circuit, coupled to the merge circuit, re-inputs a fourth portion of the primitives to the bypass processor(s) until the first portion has been rendered for a line.

Abstract: A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits x0 and x1 of the input bits and outputting a vector {x0′, x1′} such that a number of 1's at bit x0′ over time is within ±1 of a number of 1's at bit x1′. At least two 4-bit vector shufflers input the vectors {x0′, x1′}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x0′, x1′} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x0′, x1′} in the same manner as the bit shufflers operate on the bits x0 and x1. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Abstract: A system (e.g., a digital-to-analog converter (DAC)) includes a digital section and an analog section. The digital section has drivers that generate drive signals based on received digital input signals. The drive signals are received at switches in the analog section of the DAC. The switches generate analog signals therefrom. Swing values of the drive signals are limited to a predetermined amount to substantially eliminate glitch in the analog signals. The drivers can be coupled between first and second nodes that receive different power signal values. Controlling the power signal values allows for the limiting of the swing values. Limiting the swing values limits stored charged in the first and second switches, which substantially eliminates glitch in the analog signals. This can be done regardless on environmental variances (e.g., temperature variance) during operation of the DAC.

Abstract: Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes two differential transistor pairs connected together. The two differential pairs are constructed and arranged to use gates of the associated transistors as inputs to receive and combine a number of phase shifted CMOS input signals. The combined CMOS input signal are converted to CML level signals which are provided as circuit outputs.

Abstract: An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2n subranges. A first subrange of the 2n subranges is bounded by a lowest value of the range, a second subrange of the 2n subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2n subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than {1/[2(2n−1)]} of the total range. Each of the at least one remaining subrange measures less than [1/(2n−1)] of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable.

Abstract: A method and system for providing a graphical image on a display is disclosed. The display includes a plurality of pixels. The data includes a plurality of fragments for the at least one object. The plurality of fragments intersects a portion of the plurality of pixels. The method and system include defining a plurality of macro-pixels. Each of the plurality of macro-pixels includes a second portion of the plurality of pixels. The second portion of the plurality of pixels are adjacent and include n pixels of the second portion of the plurality of pixels in a first direction and m pixels of the second portion of the plurality of pixels in a second direction. The method and system further include rendering the plurality of pixels by rendering a plurality of macro-pixels in raster order. In one aspect, each macro-pixel is rendered by rendering the second portion of the plurality of pixels pixel by pixel.

Abstract: An area-efficient finite impulse response filter having permuted bit-order functional elements that provide substantially straight and direct interconnects with minimized length between adjacent elements. A functional element is coupled with an input data path and an output data path, at least one of which has a permuted bit-order data path exhibiting bit-order ordinal discontinuity. The permuted bit-order data path also can be a transposed permuted bit-order data path in which the placement of at least part of a data path is transposed, relative to prior art placements. The bit-order ordinal discontinuity fosters short, straight element interconnects which leads to increased spatial efficiency and improved performance.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and apparatus for managing defects in a memory, wherein the method includes the steps of testing a plurality of memory locations to determine an inoperable memory location and moving a memory address corresponding to the inoperable memory location to a first position in a list of available memory addresses. The method further includes the steps of incrementing an address pointer to a second position in the list of available addresses indicating a next available memory address in the list of available addresses, wherein said step of incrementing an address pointer to a second position operates to remove the memory address stored in the first position from the list of available memory addresses.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all converging at startup of the system. The operation of the startup protocol is partitioned into stages. The first stage includes the step of converging the equalizer and the timing recovery system of the slave while converging the noise reduction system of the master. Upon completion of the first stage the protocol enters a second stage which includes the step of converging the equalizer and the timing recovery system of the master, converging the noise reduction system of the slave, freezing the timing recovery system of the slave, and resetting the noise reduction system of the master.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: A radio card sized for insertion into an electronic device. The radio card includes a housing; a radio circuit disposed within the housing; an internal antenna coupled to the radio circuit; at least one external antenna contact, disposed on the housing, coupled to the radio circuit; an electrical interface, disposed on the housing at a location physically separate from that of the at least one external antenna contact; and the at least one external antenna contact and the electrical interface automatically engaging the electronic device upon insertion of the radio card into the electronic device.

Abstract: Methods for improving communication performance in a wireless communication system where the wireless communication system has at least one mobile wireless communication device and a plurality of transmitter/receiver sites. The transmitter/receiver sites have a geographic area, defined as a cell, within which the mobile wireless wireless communication devices can communicate with at least one of the transmitter/receiver sites. The methods determine when the mobile wireless communication device should rate shift or roam based on connection quality measurement data or position information such as GPS.

Abstract: Existing (already installed) plain old telephone service (POTS) wiring at a customer premises is used as the wiring infrastructure for a local area network and additionally continues to provide ordinary POTS services at the customer premises. The network signals associated with the local area network and the POTS signals delivering POTS services coexist on the POTS wiring at the customer premises using frequency division multiplexing. In additional to POTS service, the subscriber loop also provides access to xDSL (digital subscriber line) signals associated with a wide area network (WAN). Thus three distinct networks (the PSTN associated with POTS, xDSL and the LAN) coexist on a single wiring infrastructure.

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract: A balancing/unbalancing (balun) structure for operating at frequency f1 includes a microstrip printed circuit board (PCB). A balun on the PCB includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces on the PCB connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter on the PCB is wrapped around the balun and includes a first folded element with a transmission length of &lgr;2/4 and connected to the output port. A second folded element has a transmission length of &lgr;2/4 and connected to the tap point. A third folded element connects the tap point to the output port and has a transmission length of &lgr;2/4.

Abstract: A method is contemplated. According to the method, capacitances in a first resistance/capacitance (RC) extraction corresponding to a circuit are modified. Each capacitance is modified to estimate Miller effect on that capacitance. A ratio of a total capacitance on a first wire after the modification in the first RC extraction to a total capacitance on the first wire before the modification in the first RC extraction is calculated. Capacitances in a second RC extraction that are coupled to the first wire are modified according to the ratio. The second RC extraction is a reduced extraction as compared to the first RC extraction. A timing analysis is performed for the circuit using the second RC extraction with capacitances modified to estimate Miller effect.

Abstract: A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and third voltage sources. The first stage accepts input signals having a first common mode voltage range and outputs a first output signal having a second common mode voltage range and being amplified a first amount. The second stage has first and second inputs connected to the first and second outputs of the first stage, respectively. The second stage accepts input signals having a common mode voltage in the second range and outputs a second output signal having a third common mode voltage range and being amplified a second amount.