Abstract: A method of handling packets includes inserting a stack-specific tag into a packet, then processing the packet in a stack of network switches in accordance with tag information in the stack-specific tag. The stack-specific tag is then removed from the packet.

Abstract: Methods and apparatus for improving the current matching within current mirror circuits in applications such as low voltage integrated circuits. Embodiments of the present invention attempt to maintain the proper current ratio between reference and output supplies by adjusting the reference output of the current mirror. An existing reference voltage on the output side of the mirror can be used or a reference voltage can be created to be used for the voltage regulation of the reference side of the current mirror.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A one-time programming memory element, capable of being manufactured in a 0.13 &mgr;m or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write circuit, having first and second switches coupled to the capacitor, and a read circuit also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write circuit to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a substantially planar first surface of a stiffener. The first surface of a substrate is attached to a substantially planar second surface of the stiffener. The second surface of the stiffener is opposed to the first surface of the stiffener. A centrally located protruding portion on the second surface of the stiffener is opposed to the centrally located cavity. The protruding portion extends through an opening in the substrate. A wire bond is coupled from a bond pad of the IC die to a contact pad on the first surface of the substrate through a through-pattern in the stiffener. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, a notch in an edge of the recessed portion, and a notch in an edge of the opening.

Abstract: The present invention provides systems and methods for pseudo-random signal generation in a multi-carrier communications system. In embodiments, a transmitter includes a pseudo-random bit sequence (PRBS) generator and Medley signal generator. The PRBS generator can operate in at least one of the following modes: a parameter selection mode, a scrambler mode, and/or a combination mode. The Medley signal generator receives an output bit sequence from the PRBS generator. The Medley signal generator then generates a Medley signal which includes a set of Medley tones encoded based on the output bit sequence from the PRBS generator. The Medley signal is then sent over channels of a multi-carrier communication system such as an ADSL system.

Abstract: A method for flexibly configuring default values of a network device and a network device using such flexible configuration method is described. First, it is determined whether the default values are obtained through a microprocessor interface or a memory interface. When it is determined that the default values are obtained through the memory interface, a header is received from a memory through the memory interface it is determined from the header whether any default value of the network device should be updated. If the network device should be updated, then at least one configuration instruction is fetched from the memory and the at least one configuration instruction is interpreted. A register default value of the default values is changed, corresponding to the interpreted at least one configuration instruction.

Abstract: A method, system, and computer program product for in-place, lightweight Ack packet promotion is provided. The method includes receiving a new Ack packet; searching through a transmit queue for an old Ack packet that corresponds to the new Ack packet; and replacing the data in a number field, a checksum field, a window size field, and a timestamp options field of the old Ack packet with data in a number field, a checksum field, a window size field, and a timestamp options field of the new Ack packet.

Abstract: A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Abstract: A content addressable memory (10) comprising a group of content addressable cells (20) and a group of corresponding match switches (30) coupled by a first match line (36) that is switched to a first voltage in the event all of the match switches in the group are in a first state and is switched to a second range of voltages in the event one or more of the match switches in the group are in a second state. Apparatus for detecting the state of the first match line comprises a second line (56), a second transistor (58) coupled to the second line, a third transistor (66) coupled in series with the second transistor and a differential amplifier (70) arranged to detect the difference in voltage between the first match line and the second line.

Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter. A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

Abstract: A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Abstract: An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Abstract: A method for searching a table in a network switch includes the steps of dividing a primary lookup table into a first sub table and a second sub-table, searching the first sub-table with a first search engine, and simultaneously searching the second sub-table with a second search engine. A method for searching a primary address table within a network switch uses the steps of dividing the primary address table into a first and second address sub-tables, storing even numbered memory address locations from the primary address table within the first address sub-table in sorted order, and storing odd numbered memory address locations from the primary address table within the second address sub-table in sorted order. Thereafter the method includes the steps of searching the first address sub-table with a first search engine, and simultaneously searching the second address sub-table with a second search engine.

Abstract: A method of implementing a diffusion replica delay circuit is provided in a device with a device capacitance and operational characteristics. A diffusion replica capacitor is coupled to the device and is capable of storing a predetermined replica charge representative of a selected device operational characteristic, and a diffusion replica transistor is coupled with the diffusion replica capacitor, and is coupled between the diffusion replica capacitor and a charge sink. The transistor is disposed to control the magnitude of the predetermined replica charge.

Abstract: A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.

Abstract: A video and graphics system has a reduced memory mode in which video images are reduced in half in horizontal direction during decoding. The video and graphics system includes a video decoder for decoding MPEG-2 video data. The video images may not be downscaled in the horizontal direction when no bi-directionally predicted pictures are used. The video and graphics system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format. The output having an SDTV format may be recorded using a video cassette recorder (VCR) while the HDTV video is being displayed.

Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.