Patents Assigned to Broadcom
  • Publication number: 20040160249
    Abstract: A charge pump circuit includes a high-swing transconductance amplifier. A high input swing transconductance is provided in a negative feedback loop of the charge pump circuit without an abrupt change in transconductance. The high-swing transconductance amplifier includes a transconductance cell and high-swing circuitry. The transconductance cell includes a current supply transistor, which provides current for transconductance while input voltages are within the operational range for the transconductance cell. When the input voltages increase so as to be outside of the operational range, the current source transistor enters into triode region of operation, and provides reduced current. The high-swing circuitry supplies the current in this case so that abrupt change in transconductance does not occur.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 19, 2004
    Applicant: Broadcom Corporation
    Inventor: Ka Lun Choi
  • Publication number: 20040160272
    Abstract: A design of integrated circuit components to prevent accidental turn on when large input signals are accepted. With integrated circuits operated at lower power supply voltages, input signals having large peak values can tend to turn on devices within the integrated circuit erroneously. By placing amplifiers within the integrated circuits where input signals are received and removing the power of such amplifiers, accidental turn on can be minimized.
    Type: Application
    Filed: February 18, 2004
    Publication date: August 19, 2004
    Applicant: Broadcom Corporation
    Inventor: Arya Reza Behzad
  • Publication number: 20040163120
    Abstract: A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a subscriber to a headend. Synchronization of a clock of the subscriber with respect to a clock of the headend is enhanced using a message transmitted from the headend to the subscriber which is indicative of an error in a subscriber transmission time with respect to the time slot. A feedback loop process is used to determine at least one of fractional symbol timing correction and carrier phase correction of a transmission from the subscriber to the headend. Filter coefficients are generated at the headend from a ranging signal transmitted from the subscriber to the headend and transmitting the filter coefficients from the headend to the subscriber, the filter coefficients being used by the subscriber to compensate for noise in a transmission from the subscriber to the headend.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 19, 2004
    Applicant: Broadcom Corporation
    Inventors: Theodore F. Rabenko, James C. H. Thi, John D. Horton, Thomas J. Quigley, Lisa V. Denney, Jonathan S. Min, Christopher R. Jones, Henry Samueli, Fang Lu, Feng Chen, Sean F. Nazareth
  • Patent number: 6778602
    Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: August 17, 2004
    Assignee: Broadcom Corporation
    Inventors: Oscar E. Agazzi, John L. Creigh, Mehdi Hatamian, Henry Samueli, David E. Kruse, Arthur Abnous
  • Patent number: 6778611
    Abstract: A method for modulating a sequence of data symbols such that the transmit signal exhibits spectral redundancy. Null symbols are inserted in the sequence of data symbols such that a specified pattern of K data symbols and N-K null symbols is formed in every period of N symbols in the modulated sequence, N and K being positive integers and K being smaller than N.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: August 17, 2004
    Assignee: Broadcom Corporation
    Inventor: Gottfried Ungerboeck
  • Patent number: 6779050
    Abstract: A system and method for hardware based reassembly of a fragmented packet is shown. The method includes receiving a bandwidth request to transfer a data packet from the data provider. Then, bandwidth is allocated to the data provider, where the allocated bandwidth is less than the requested bandwidth. Next, the present invention receives part of the data packet in the allocated bandwidth from the data provider, where the part of the data packet includes a fragment header, and the fragment header includes a sequence number for the part of the data packet. The part of the data packet is then stored in external memory. Finally, the data packet is reassembled by concatenating in the correct sequence the part of the data packet with other parts of the data packets to create the reassembled data packet.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 17, 2004
    Assignee: Broadcom Corporation
    Inventors: John D. Horton, Niki R. Pantelias
  • Patent number: 6778594
    Abstract: A communications receiver architecture characterized by a relatively low intermediate frequency (IF) and a polyphase filter. The receiver includes an input amplifier coupled to a carrier signal. Respective I and Q demodulators are coupled to the output of the input amplifier. A quadrature local oscillator (LO) generator provides respective LO_I and LO_Q inputs to the I demodulator and LO_Q inputs to the I demodulator and to the Q demodulator. The quadrature LO generator is driven by a phase-locked LO, and the LO frequency is such that an IF of, in one embodiment, approximately 1 MHz results. The I demodulator and Q demodulator outputs are applied through respective A/D converters to a polyphase filter. The polyphase filter outputs are then processed by a digital I/Q demodulator.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: August 17, 2004
    Assignee: Broadcom Corporation
    Inventor: Bin Liu
  • Publication number: 20040157379
    Abstract: An anti-fuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A channel is formed between the source and drain regions. A gate and gate oxide are formed on the channel and lightly doped source and drain extension regions are formed in the channel. The lightly doped source and drain regions extend across the channel from the source and the drain regions, respectively, occupying a substantial portion of the channel. Programming of the anti-fuse is performed by application of power to the gate and at least one of the source region and the drain region to break-down the gate oxide, which minimizes resistance between the gate and the channel.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventors: Akira Ito, Douglas D. Smith, Myron J. Buer
  • Publication number: 20040156250
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Publication number: 20040155683
    Abstract: Methods and systems for sensing load conditions and for adjusting output current drive according to the sensed load conditions to maintain one or more signal characteristics within a desired range. Load conditions are sensed by monitoring one or more signal characteristics that are affected by load conditions, such as voltage changes with respect to time. Output current drive is then adjusted, as needed, to maintain the one or more desired signal characteristics. In an embodiment, rising and/or falling edge slopes are monitored. For example, a dV/dt may be monitored. The dV/dt can be monitored by coupling a capacitance to the output signal, generating a current with the capacitance, and generating a voltage from the current. The voltage is generally proportional to the dV/dt. Depending upon the load conditions, a supplemental current is generated and/or adjusted and added to the output signal to maintain the desired signal characteristics within a desired range.
    Type: Application
    Filed: November 12, 2003
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventor: Janardhanan S. Ajit
  • Publication number: 20040155807
    Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output ofthe coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.
    Type: Application
    Filed: July 24, 2003
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
  • Publication number: 20040156323
    Abstract: An arbiter circuit is provided for resolving a plurality of N request signals received from a plurality of agents requesting access to a resource.
    Type: Application
    Filed: January 20, 2004
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventor: Jun Cao
  • Publication number: 20040158657
    Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
    Type: Application
    Filed: December 31, 2003
    Publication date: August 12, 2004
    Applicant: Broadcom Corporation
    Inventors: Afshin Momtaz, Xin Wang, Jun Cao, Armond Hairapetian, David Chung
  • Patent number: 6774910
    Abstract: A method and system for providing antialiasing of a graphical image on a display from data describing at least one object is disclosed. The display includes a plurality of pixels. The method and system include providing a plurality of fragments for the at least one object. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments includes a depth value, a slope of the depth value, and an indication of a portion of a corresponding pixel that is intersected. The method and system include calculating a plurality of subpixel depth values for a fragment of the plurality of fragments. The plurality of subpixel depth values is calculated using the depth value and the slope of the depth value of the fragment. The method and system include determining whether to store a portion of the fragment based on the plurality of subpixel depth values for the fragment and the indication of the extent the corresponding pixel is intersected by the fragment.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Broadcom Corporation
    Inventor: Michael C. Lewis
  • Patent number: 6775521
    Abstract: A method for identifying a bad GSM speed frame and simultaneously maintaining a frame erasure rate below a specified value. The method is based upon a joint use of four signal quality metrics: (1) frame CRC parity check; (2) estimated burst signal-to-noise ratio; (3) estimated frame bit error count; and (4) stealing flag values of a frame. Another feature includes providing an improved estimated burst signal-to-noise ratio.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: August 10, 2004
    Assignee: Broadcom Corporation
    Inventor: Yue Chen
  • Patent number: 6775667
    Abstract: A method and system for sorting a number of items in a computer system is described. The sort is based on values of a key. Each item has a value. The method and system include providing stages, providing switch(es) coupled between the stages, and providing a final switch coupled with a last stage. Each stage has a pair of first-in-first-out buffers (FIFOs) that store twice as many of the items as the FIFOs in a previous stage. The switch merges and sorts a first portion of the number of items from the pair of FIFOs in the previous stage based on the key and provides the first portion of the number of items to a first FIFO of the stage in order. The switch performs an analogous function for a second FIFO in the stage. The last switch merges and sorts a third portion of the number of items to provide the number of items in order.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: August 10, 2004
    Assignee: Broadcom Corporation
    Inventors: Michael C. Lewis, Aleksandr Movshovich
  • Patent number: 6775334
    Abstract: Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: August 10, 2004
    Assignee: Broadcom Corporation
    Inventors: Tian-Min Liu, Loke Kun Tan, Steven T. Jaffe
  • Patent number: 6774830
    Abstract: Methods and systems for applying digital dither includes methods and systems for applying digital dither in data converters, such as, for example, delta-sigma data converters. In an embodiment, an analog signal from a first path of a delta-sigma modulator is quantized to an m-bit digital signal and an n-bit dithered digital feedback signal is generated from at least a portion of the m-bit digital signal. The n-bit dithered digital feedback signal is converted to an analog feedback signal and fed back to a second path of the delta-sigma modulator. In an embodiment, the n-bit dithered digital feedback signal is generated by selecting one of a plurality of sets of n-bits from the m-bit digital signal depending upon a state of a dither control signal. The dither control signal can alternate between a plurality of states or pseudo-randomly switch between a plurality of states.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: August 10, 2004
    Assignee: Broadcom Corporation
    Inventor: Todd Lee Brooks
  • Publication number: 20040153681
    Abstract: Methods and circuits for phase detectors having extended linear and monotonic ranges of operation. Phase detectors consistent with the present invention include a REFERENCE output that has improved immunity to the timing relationship between data input and clock signals. This improved immunity results in extended linear and monotonic ranges of operations.
    Type: Application
    Filed: November 12, 2002
    Publication date: August 5, 2004
    Applicant: Broadcom Corporation
    Inventor: Jun Cao
  • Publication number: 20040150487
    Abstract: A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is replaced by an air core under the differential signal traces.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Applicant: Broadcom Corporation
    Inventor: Mohammad Tabatabai