Abstract: Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.

Abstract: Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

Abstract: A system is provided for correcting start-up deficiencies in an amplifier. The system includes a comparing device configured to (i) receive a second circuit node voltage and a reference voltage as inputs, (ii) compare the received second circuit node voltage and the reference voltage, and (iii) produce a compensating voltage signal based upon the comparison. Next, an active device has a control terminal connected to an output port of the comparing device and is configured to receive the compensating voltage signal. The active device also includes an output terminal connected to the control terminal of the second active device, and a common terminal connected to a first circuit node. Another active device has a control terminal connected to the output port of the comparing device and is configured to receive the compensating voltage signal. The other active device also has an output terminal connected to the control terminal of the first active device, and a common terminal connected to the first circuit node.

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: A method and apparatus for coupling a voiceband modem circuit to a common phoneline connector, the common phoneline connection having a ring line connection and a tip line connection which couples a ring/tip line pair to a subscriber loop circuit, the voiceband modem circuit operating in a voiceband modem operating frequency band and having a voiceband modem interface ring line and a voiceband modem interface tip line. The voiceband modem interface ring line is coupled to the ring line and the voiceband modem interface tip line is coupled to the tip line connection by inserting, between the ring line connection and the voiceband modem interface ring line and between the tip line connection and the voiceband modem interface tip line, a series pair of inductors. A first inductor of the series pair has a low inductance and a high self-resonant frequency and a second inductor of the series pair has a high inductance and low self-resonant frequency.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: A charge pump includes at least one switching transistor for switching current on or off in response to an up or down signal, a pair of transistors (one coupled to the source and the other to the drain of the switching transistor) each having its source and drain shorted and coupled to receive a complement of the signal on the gate terminal of the switching transistor on their gate terminals, and a fourth transistor coupled to the drain of the switching transistor and a power supply. The pair of transistors are activated concurrent with the deactivation of the switching transistor. The fourth transistor may provide for active shutoff of a current transistor being switched by the switching transistor, by actively charging the source of the current transistor to a voltage which is not exceeded by the gate terminal of the current transistor.

Abstract: An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance, substantially noise-free DC voltage or signal source.

Abstract: A clock divider circuit producing 0° and 90° outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a pair of cross-coupled circuits. The clock divider circuit may produce a first output clock signal and a second output clock signal that is phase shifted a positive 90° with respect to the first output clock signal. The operation of the circuit may be responsive only to the input clock signal. In other words, the circuit may not require a reset signal to operate in a deterministic fashion.

Abstract: A decoder having a memory structure which receives and stores potential symbols, with each of the potential symbols having a unique pointer associated therewith. One of the potential symbols is a most likely symbol. The most likely symbol is selected using a pointer selector which processes the unique pointers according to a predetermined selection operation and selects the most likely pointer which, in turn, is uniquely associated with the most likely symbol. The most likely pointer then is used to produce the most likely symbol. The pointer selector is a shuffle exchange network and the predetermined selection operation is a shuffle-exchange operation. The decoder can be used in systems that conform to IEEE Standard 802.3ab, e.g., gigabit Ethernet systems. The potential symbols are four-dimensional, 12-bit symbols having eight symbol states. The memory structure and pointer selector can be constituent of a maximum likelihood decoder, for example a trellis decoder, more specifically a Viterbi decoder.

Abstract: In a Noise Feedback Coding (NFC) system having a corresponding ZERO-STATE filter structure, the first ZERO-STATE filter structure including multiple filters, a method of producing a ZERO-STATE response error vector. The method includes: (a) transforming the first ZERO-STATE filter structure to a second ZERO-STATE filter structure including only an all-zero filter, the all-zero filter having a filter response substantially equivalent to a filter response of the ZERO-STATE filter structure including multiple filters; and (b) filtering a VQ codevector with the all-zero filter to produce the ZERO-STATE response error vector corresponding to the VQ codevector.

Abstract: In a Noise Feedback Coding (NFC) system operable in a ZERO-STATE condition and a ZERO-INPUT condition, the NFC system including at least one filter having a filter memory, a method of updating the filter memory. The method comprises: (a) producing a ZERO-STATE contribution to the filter memory when the NFC system is in the ZERO-STATE condition; (b) producing a ZERO-INPUT contribution to the filter memory when the NFC system is in the ZERO-INPUT condition; and (c) updating the filter memory as a function of both the ZERO-STATE contribution and the ZERO-INPUT contribution.

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is processed by a digital filter. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. DAC line driver cells are adaptively configurable to operate in either a class-A or a class-B mode depending on the desired operational modality. A discrete-time analog filter is integrated with the DAC line driver to provide additional EMI emissions suppression. An adaptive electronic transmission signal cancellation circuit separates transmit data from receive data in a bidirectional communication system operating in full duplex mode.

Abstract: A printed bandpass filter is mounted on a precision substrate to eliminate the need for post-fabrication tuning. The filter input is capacitively coupled to a series of quarter wavelength resonators and the filter output. The quarter wavelength resonators are printed as spirals to reduce filter size. The resonators define the bandpass characteristics of the filter. The filter also weakly couples the input signal to the filter output in a manner to cancel the signal image. Mechanical clips mitigate thermal stress on solder connections when the precision substrate mounted on a second printed circuit board.

Abstract: A bandpass filter includes a plurality of resonators on a printed circuit board. An input pin is connected to a first resonator of the plurality of resonators. An output pin is connected to a second resonator of the plurality of resonators. The first and second resonators are magnetically coupled to each other. The first and second resonators are coupled to other resonators using mixed coupling. The other resonators are coupled to each other using electric coupling.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to he saturation signal.

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.