Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.

Abstract: A method to eliminate discontinuities in an adaptively filtered signal includes filtering a beginning portion of a current signal frame using a past set of filter coefficients, thereby producing a first filtered frame portion. The method also includes filtering the beginning portion of the current signal frame using a current set of filter coefficients, thereby producing a second filtered frame portion. The method also includes modifying the second filtered frame portion with the first filtered frame portion so as to smooth a possible filtered signal discontinuity between the second filtered frame portion and a past filtered frame produced using the past filter coefficients.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2n subranges. A first subrange of the 2n subranges is bounded by a lowest value of the range, a second subrange of the 2n subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2n subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than {1/[2(2n−1)]} of the total range. Each of the at least one remaining subrange measures less than [1/(2n−1)] of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable.

Abstract: A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a distinct data path through the adder. For each set of numbers, the system further includes a logic gate for inhibiting a carry path, from each portion of the adder corresponding to each carry path, to a next adjacent carry path. The system isolates two or more contiguous data paths through the fixed-width adder corresponding to each of the two or more sets of two binary numbers. The invention prevents unwanted signals from crossing summing lane boundaries in different processing modes. The same adder logic can thus be used for each processing mode by varying the combination of mode select control signals.

Abstract: A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted.

Abstract: A method of processing a decoded speech (DS) signal including successive DS frames, each DS frame including DS samples. The method comprises: adaptively filtering the DS signal to produce a filtered signal; gain-scaling the filtered signal with an adaptive gain updated once a DS frame, thereby producing a gain-scaled signal; and performing a smoothing operation to smooth possible waveform discontinuities in the gain-scaled signal.

Abstract: A filter controller processes a decoded speech (DS) signal. The DS signal has a spectral envelope including a first plurality of formant peaks having different respective amplitudes. The controller produces, from the DS signal, a spectrally-flattened DS signal that is a time-domain signal. The spectrally-flattened time-domain DS signal has a spectral envelope including a second plurality of formant peaks. Each of the second plurality of formant peaks approximately coincides in frequency with a respective one of the first plurality of formant peaks. Also, the second plurality of formant peaks have approximately equal respective amplitudes. Next, the controller derives, from the spectrally-flattened time-domain DS signal, a set of filter coefficients representative of a filter response that is to be used to filter the DS signal.

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay.

Abstract: In a communications receiver for quadrature demodulation, a feedback technique for reducing the image response of the receiver. The communications receiver includes an I demodulator and a Q demodulator. A local oscillator (LO) signal is provided by a PLL to a quadrature LO generator that provides an LO_I signal to an I demodulator and an LO_Q signal to a Q demodulator. The LO_I and LO_Q signals are amplitude and phase-controlled versions of the LO signal. An image/signal ratio (I/S) detector detects the relative phase difference and the relative amplitude difference between the respective output terminals of the I demodulator and the Q demodulator and applies an amplitude control signal and a phase control signal to corresponding amplitude control and phase control inputs of the quadrature LO generator. The I/S detector calibrates the quadrature LO generator during the interstitial interval between the reception of data packets.

Abstract: A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.

Abstract: A method of performing an excitation Vector Quantization (VQ) in a Noise Feedback Coding environment involves reorganizing a calculation of an energy of an error vector for each of a plurality of candidate excitation vectors of a codebook. The energy of the error vector is a cost function that is minimized during a search of the codebook for a best candidate excitation VQ vector. The reorganization includes expanding a Mean Squared Error (MSE) term of the error vector, excluding an energy term that is invariant to the candidate excitation vector, and pre-computing energy terms of ZERO-STATE responses of the candidate excitation vectors that are invariant to sub-vectors of a subframe. Another method searches a signed codebook. Both methods use correlation techniques.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A quantizer for quantization of a vector comprises a codevector generator that generates a set of candidate codevectors and a memory for storing an illegal space definition representing illegal vectors. The quantizer also includes a legal status tester that determines legal candidate codevectors among the set of candidate codevectors using the illegal space definition, and a codevector selector that determines a best legal candidate codevector among the one or more legal candidate codevectors. The vector includes parameters relating to a speech and/or audio signal, such as Line Spectral Frequencies (LSFs).

Abstract: A system and method for providing a sort in a computer system is disclosed. The sort is based on a plurality of values of a key. Each of the plurality of items has an associated value of the plurality of values. The method and system include providing a new item of the plurality of items to a plurality of sort cells. The new item includes a new value of the plurality of values. The plurality of sort cells is for sorting the plurality of items. Each sort cell is for sorting a corresponding item of the plurality of items. The corresponding item has a corresponding value of the plurality of values. The method and system further include comparing the new value to the corresponding value for each of the plurality of sort cells to determine whether to retain the corresponding item. Each of the plurality of sort cells retains the corresponding item if the corresponding item is to be retained.

Abstract: A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.

Abstract: A method of searching a signed codebook to quantize a vector includes weighting a shape codevector in a set of shape codevectors with a weighting function for a Weighted Mean Square Error (WMSE) criteria, to produce a weighted shape codevector. The method further includes correlating the weighted shape codevector with the vector to produce a weighted correlation term. The method also includes determining, based on a sign of the weighted correlation term, a preferred one of a positive and a negative signed codevector associated with the shape codevector. The method further includes determining whether one of the signed codevectors does not belong to an illegal space defining illegal vectors.

Abstract: A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of the operation. The status of the condition setting indicator determines whether or not multibit condition codes are set. When they are to be set, they are set depending on the results of carrying out the operation for each lane.

Abstract: The present invention is drawn to a network device configured to prevent data misalignment of a data packet containing extra header bytes. The network device includes an ingress module having an input interface to receive data. A header detector configured to detect the header bytes of the cell and remove the header from the cell of the data packet is also provided on the network device. A counter determines whether the cell of the data packet contains a multiple of a predetermined bytes. If the counter determines that the cell of the data packet does not satisfy the multiple of the predetermined bytes, an insertion module inserts null bytes into the cell of the data packet to form a modified cell of the data packet. Then, an extraction module removes the null bytes from the modified cell of the data packet when the modified cell exits the network device.