Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: An agent, in response to a write to a shared block, is configured to initiate a read exclusive transaction on an interface on which the agent communicates. Additionally, the agent is configured to indicate, to a responding agent or agents on the interface, that a data transfer is not required from the responding agent or agents in response to the read exclusive transaction. In one embodiment, the agent indicates to the responding agents that a data transfer is not required in a response phase of the transaction. Specifically, the agent may respond in such a way that the agent indicates that it will provide the data (i.e. that the agent will provide the data to itself). For example, the agent may respond with an exclusive ownership indication. On the interface for such an embodiment, an exclusive ownership response may require that the agent having exclusive access respond with the data.

Abstract: A cache includes an error circuit for detecting errors in the replacement data. If an error is detected, the cache may update the replacement data to eliminate the error. For example, a predetermined, fixed value may be used for the update of the replacement data. Each of the cache entries corresponding to the replacement data may be represented in the fixed value. In one embodiment, the error circuit may detect errors in the replacement data using only the replacement data (e.g. no parity or ECC information may be used). In this manner, errors may be detected even in the presence of multiple bit errors which may not be detectable using parity/ECC checking.

Abstract: A wide input range amplifier includes a first and second stage. The first stage has first and second inputs, first and second outputs, and first, second and third voltage sources. The first stage accepts input signals having a first common mode voltage range and outputs a first output signal having a second common mode voltage range and being amplified a first amount. The second stage has first and second inputs connected to the first and second outputs of the first stage, respectively. The second stage accepts input signals having a common mode voltage in the second range and outputs a second output signal having a third common mode voltage range and being amplified a second amount.

Abstract: An apparatus includes a plurality of memories, a plurality of systems, and a switch interface circuit. Each of the plurality of systems includes a memory controller coupled to a respective one of the plurality of memories. Additionally, each of the plurality of systems is coupled to at least one other one of the plurality of systems. Each of the plurality of systems further includes one or more coherent agents configured to access the plurality of memories, and wherein the plurality of systems enforce coherency across the plurality of systems for at least some accesses. At least one of the plurality of systems is coupled to the switch interface circuit separate from the interconnection of the plurality of systems. The switch interface circuit is configured to interface the apparatus to a switch fabric.

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract: A differential driver includes a switching module and first and second voltage controlled voltage sources. The switching module has a plurality of switches each controlled by an input signal, a first voltage input and a second voltage input, and a signal output. The first voltage controlled voltage source is connected to the first voltage input. The first voltage controlled voltage source has a low impedance. The second voltage controlled voltage source is connected to the second voltage input. The second voltage controlled voltage source also has a low impedance. The switching circuit outputs an output signal having an output voltage and current controlled by the first and second voltage controlled voltage sources. The output signal is based upon the input signal.

Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Abstract: An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

Abstract: An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

Abstract: The present invention generally relates to voltage-controlled oscillators. More specifically, the present invention relates to method and circuitry for implementing a differentially tuned varactor-inductor oscillator. In one exemplary embodiment, the present invention includes an LC tank circuit having a couple of terminals, a first and second capacitors, and a first and second varactors. The first and second varactors are connected in series forming a first and a second node. The first capacitor connects the first node and one terminal of the LC tank circuit. The second capacitor connects the second node and the other terminal of the LC tank circuit. A pair of differential input control signals is applied across the first and the second varactors, respectively, to tune the LC tank circuit thereby generating an oscillator output.

Abstract: An oscillator having multi-phase complementary outputs comprises a first plurality of single ended amplifiers connected in series to form an input and an output and a second plurality of single ended amplifiers connected in series to form an input and an output. The first and second plurality have the same odd number of amplifiers, A first feedback path connects the output to the input of the first plurality of amplifiers to establish oscillations in the first plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the first plurality. A second feedback path connects the output to the input of the second plurality of amplifiers to establish oscillations in the second plurality of amplifiers at a frequency dependent upon the delay time from the input to the output of the second plurality.

Abstract: A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information including an opcode value. The opcode value allows the fabric to determine the packet type, sucha a whether the packet is a broadcast packet, a unicast packet, a multicast packet, etc. Based on the opcode value read, a particular forwarding table of a plurality forwarding tables is read and an egress port bitmap is determined based on entries read from the particular forwarding table. The incoming data packet is then forwarded based on the egress port bitmap. In addition, the architecture of the switch fabric is also disclosed.

Abstract: A method and apparatus for frequency shift-keying (FSK) demodulation includes processing that begins by generating a charge signal, a data acquisition signal, and a reset signal from an I component and a Q component of an FSK modulated signal. The processing continues by generating a delta frequency signal based on the charge signal, the data acquisition signal, and the reset signal. The delta frequency signal is representative of the frequency difference used within the FSK modulation to indicate a logic 1 and a logic 0. The processing then continues by demodulating the delta frequency signal to recapture a stream of data.

Abstract: A VCO for a PLL may include a ring oscillator having a power supply controlled in response to the VCO's control voltage input and an inverter having an input coupled to the ring oscillator's output and also supplied with a power supply controlled by the control voltage input. Together, the output of the ring oscillator and the output of the inverter may closely approximate a differential signal. The VCO may include an amplifier for amplifying a differential input to an output in the voltage domain of the system including the PLL. The output of the ring oscillator may be used as an input to the amplifier, and the output of the inverter may be used as the other input. The power supply terminals of the ring oscillator and the inverter may be coupled to outputs of a current mirror. In one implementation, the current mirror may not be cascoded.

Abstract: A SLIC assembly includes high voltage operational amplifiers (op amps) and low voltage op amps. The high voltage op amps are used to drive ring and tip signals while the low voltage op amps are used to drive other signals. The low voltage op amps include Class A-B amplifier drivers based on bipolar transistors. Bipolar transistors are also provided as bias compensating diodes for bias point stabilization over dynamic operating conditions such as temperature. The high voltage op amps include a composite MOSFET-bipolar complimentary symmetry driver stage that offers the bias control and stability of a bipolar device topology and drive capabilities of a power MOSFET device.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A data switch for network communications includes a data port interface which supports at least one data port which transmits and receives data. The switch also includes a CPU interface, where the CPU interface is configured to communicate with a CPU, and a memory management unit, including a memory interface for communicating data from the data port interface to the switch memory. A communication channel is also provided, communicating data and messaging information between the data port interface, the CPU interface, the switch memory, and the memory management unit. The data port interface also includes an access control unit that filters the data coming into the data port interface and takes selective action on the data by applying a set of filter rules such that access to the switch is controlled by the set of filter rules.

Abstract: The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

Abstract: A varactor folding technique reduces noise in controllable electronic oscillators through the use of a series of varactors having relatively small capacitance. A folding circuit provides control signals to the varactors in a sequential manner to provide a relatively smooth change in the total capacitance of the oscillator. Consequently, effective control of the oscillator is achieved with accompanying reductions in oscillator noise such as flicker noise.