Abstract: A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

Abstract: A packet switching fabric includes a data ring, a control ring, a plurality of network links each coupled to at least one network node, and a plurality of switching devices coupled together by the data ring and the control ring so that the network links can be selectively communicatively coupled.

Abstract: A queue length arbiter system provides for selecting from a plurality of N queues requiring access to a resource. The system includes: an arbitration circuit; and a plurality of weight circuits each being associated with a corresponding one of the queues, and being operative to store a corresponding weight count value, and also being operative to initialize the corresponding weight count value to a corresponding initial weight value determined based on a length value indicative of a number of data portions enqueued at the corresponding queue at an initial time, and being further operative to decrease the corresponding weight count value in response to a corresponding one of a plurality of grant signals, and also being operative to generate a corresponding one of a plurality of weight count signals, the corresponding weight count signal carrying the corresponding weight count value.

Abstract: A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.

Abstract: A management system has a hierarchical structure of interconnected management authorities controlling communication network resources. The system also includes user interfaces. Each authority has a number of agents which communicate internally with other agents and externally with other agents in a uniform manner using KQML semantics. Agents may be intelligent or simply reactive. Generally, reactive agents are located within a platform part of an authority and intelligent agents are located within the controlling part of an authority. Agents within the controlling part are grouped into functional components to provide FCAPS functionality.

Abstract: A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal.

Abstract: Requests are processed to transmit data packets upstream from a cable modem to a cable headend in a manner that minimizes the use of CPU operations and/or memory capacity. Data packets to be transmitted upstream are stored at the cable modem. The data packets each have a given transmission data byte length value. Burst profiles are received successively at the cable modem. Each time a new bust profile is received, a set of physical data length values corresponding to respective transmission data byte length values is calculated from the parameters of the received burst profile. The calculated set of physical data length values is stored in memory so the individual values can be retrieved from the transmission data byte length values again and again, rather than being re-calculated each time a conversion is made from transmission data byte length values to physical data length values. The same set of physical data length values is used until a new burst profile is received by the cable modem.

Abstract: The drift between a write pointer and a read pointer processing packets of data through a FIFO buffer is compensated for by adjusting the start of the read pointer relative to the write pointer. The FIFO buffer is sized to include a number of storage cells equal to the product of the maximum frequency offset between the write clock and read clock and the maximum number of data units in a packet. Initially the start of the read pointer is delayed, relative to the write pointer, by a portion of the number of storage cells in the FIFO. During the processing of a data packet it is determined whether the read pointer is drifting toward or away from the write pointer. If the read pointer is drifting away from the write pointer, for subsequent data packets, the read pointer is started almost immediately after the write pointer writes to the first storage cell in the FIFO.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths. The ALUs of the data path are coupled using a carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating a signal in response to a carry bit received over the carry chain, the signal comprises a saturation signal and a saturation value. The saturation signal is generated using logic that tests for saturation in the data path. The ALUs of the data path are further coupled using a right-going carry chain for transmitting the saturation signal back down the data path. The saturation signal is transmitted from the MSB ALU through the ALUs of the data path to the LSB ALU using a first back propagation channel.

Abstract: A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM and VSB symbols, which are expressed in two's compliment notation, include an extra bit required to compensate for a fixed offset term introduced by the two's compliment numbering system. A decision feedback equalizer includes a decision feedback filter section which operates on symbolic decisions represented by a wordlength which excludes the added bit representing the offset. The vestigal word is convolved with the decision feedback filter's coefficients, while a DC component, corresponding to the excluded bit, is convolved with the same coefficient values in a correction filter. The two values are summed to provide an ISI compensation signal at the input of a decision device such as a slicer. A DC component representing a pilot tone in VSB transmission systems also introduces a DC component, and additional bits, to a VSB wordlength.

Abstract: A method and a system for decoding information signals encoded by a multi-state encoding architecture and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are detected in a symbol decoder, implemented using look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in one of two disjoint symbol-subsets. The symbol decoder is implemented as a pair of slicers, each detecting an input signal with respect to one of two disjoint symbol-subsets. A third slicer detects the input with respect to the union of the two disjoint symbol-subsets. Decisions from the first, second and third slicers are processed to define 1D square error terms expressed in Hamming metrics. Reduced bit count error terms allow follow-on error processing to be performed with a minimum of computational complexity.

Abstract: Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

Abstract: An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum.

Abstract: A method for refreshing data in a circuit element included in a dynamic register. A static loop is coupled to the circuit element as a feedback path from the output terminal to the input terminal of the circuit element. A control signal is provided to the static loop. The static loop is activated via the control signal to refresh the data in the circuit element.

Abstract: A detector circuit for determining whether synchronization lock has been optimally achieved in feedback-type control systems. The detector circuit evaluates an error signal developed by a phase/frequency detector and compares the absolute magnitude of the error signal to a first threshold signal corresponding to a magnitude metric. When the value of the error signal is less than the magnitude threshold value, an event signal initiates a time interval counter which continues counting so long as the error signal remains below the magnitude threshold value. The time interval counter continues until it counts to a second threshold value corresponding to a timing metric. At this point, synchronization lock is declared.

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.

Abstract: A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as a slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The operation of the startup protocol is partitioned into three stages. During the first stage the timing recovery system and the equalizer of the slave are trained and the noise reduction system of the master is trained. During the second stage the timing recovery system of the master is trained in both frequency and phase, the equalizer of the master is trained and the noise reduction system of the slave is trained. During the third stage the noise reduction system of the master is retrained, the timing recovery system of the master is retrained in phase and the timing recovery system of the slave is retrained in both frequency and phase.

Abstract: A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.