Abstract: A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

Abstract: A system and method for providing antialiasing of a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of pixels. The at least one object includes a plurality of fragments. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments including an indication of a portion of a corresponding pixel that is intersected. The system and method include providing at least one active region for the pixel. The at least one active region intersects a first portion of the pixel. The method and system also include providing at least one new region. A first portion of the at least one new region indicates where in the pixel the at least one active region and the fragment intersect. A second portion of the at least one new region indicates where in the pixel the at least one active region and the fragment do not intersect.

Abstract: The invention is table search device having a table that has a plurality of entries and a cache having a subset of entries of the plurality of entries of the table. A search engine is configured to first search the cache in a first number of search cycles and then search the table in a second number of search cycles based on search results of the cache. The search engine connected to the table and the cache.

Abstract: An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum.

Abstract: A switch using indicators for address learning. The switch has a first activator configured to control a first indicator to indicate when a source address needs to be learned and when a source address has been learned. A second activator is configured to control a second indicator to indicate when a destination address has not been learned and when a destination address has been learned. Finally, a third activator is configured to control a third indicator to indicate when a source address has not been learned in all switches.

Abstract: Digital packets, defined by a sync byte and then 130 MPEG2 compressed QPSK signal bytes, from a satellite transponder are reformatted prior to transmission to television receivers in apartments in a building wired to distribute video signals. A side byte between such sync and signal bytes in each packet indicates (a) any QPSK packet uncorrectable error and (b) processing information which allows automatic reconfiguration at the settop box. Additional FEC bytes correct to 8 errors within a MPEG2QPSK packet. The system removes the FEC bytes and reframes the MPEG2QPSK packets into a superpacket by converting a first number of the MPEG2QPSK packets to a second number of MPEG2QAM packets. An added sync byte indicates the beginning of each such MPEG2QAM packet. The system adds side data bytes including any uncorrectable errors in each MPEG2QPSK packet and adds a new, less complicated FEC to each MPEG2QAM packet.

Abstract: A bistable device has first and second complementary input terminals and first and second bistable states that are determined by the polarity of the signal applied to one of the input terminals. A source of an uninverted binary input signal, preferably an uninverted data stream, has a first value or a second value. A source of an inverted binary input signal, preferably an inverted data stream, has a first value or a second value in complementary relationship to the values of the uninverted input signal. A first source of a trigger signal has one polarity. A second source of a trigger signal has the other polarity. The first trigger signal is applied to the first input terminal and the second trigger signal is applied to the second input terminal to drive the bistable device into the first stable state when the input signal has the first value.

Abstract: A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus. A system memory coupled to the system bus arranged to store a secret key array associated with the data and a central processing unit coupled to the system bus wherein encryption accelerator uses substantially no central processing unit resources to execute the encryption algorithm.

Abstract: A communications network switch includes a plurality of network ports for transmitting and receiving packets to and from network nodes via network links, each of the packets having a destination address and a source address, the switch being operative to communicate with at least one trunking network device via at least one trunk formed by a plurality of aggregated network links. The communications network switch provides a method and apparatus for balancing the loading of aggregated network links of the trunk, thereby increasing the data transmission rate through the trunk.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: A switch is configured to block packets from being transmitted through designated ports. The switch has port bitmap generator configured to obtain a port bitmap and a table is configured to store a block mask indicating which port the packet should not be transmitted. A block mask lookup is configured to determine the block mask for the packet from the table, and a transmit port bitmap generator is configured to determine which ports the packet should be transmitted using the port bitmap and the block mask.

Abstract: A switch assembly having multiple blades in a chassis and a method of using that assembly to switch data is disclosed. A network switch assembly for network communications includes at least one fabric blade and a plurality of port blades. The at least one fabric blade has at least one switch having a plurality of data port interfaces, supporting a plurality of fabric data ports transmitting and receiving data, and a CPU interface, where CPU interface is configured to communicate with a CPU. The at least one fabric blade also has a CPU subsystem communicating with the CPU interface. Each of said plurality of port blades has at least one switch having a plurality of data port interfaces, supporting a plurality of port data ports transmitting and receiving data.

Abstract: A method for reducing system performance degradation caused by switching noise in a system which includes a set of subsystems. Each of the subsystems includes an analog section and a digital section. Each of the analog sections operates in accordance with a corresponding one of a set of sampling clock signals which are synchronous in frequency. The digital sections operate in accordance with a receive clock signal. The receive clock signal is generated such that it is synchronous in frequency with the sampling clock signals and has a phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Abstract: A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

Abstract: A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory.

Abstract: The present invention relates to electrostatic discharge (ESD) protection and, more particularly, to methods and systems for improving response times of ESD triggering and clamping circuitry. An ESD protection circuit protects ESD circuitry from direct current (DC) voltage stress during normal operations by reducing terminal pad voltage level. A frequency bypass circuit implemented across an ESD protection circuit essentially acts as a short circuit during ESD events and essentially acts as an open circuit during normal operations. A frequency bypass circuit implemented in conjunction with an ESD protection circuit enables ESD triggering and clamping circuitry to react to ESD events without undue delay. Unlike an ESD protection circuit, a frequency bypass circuit does not result in substantial voltage reduction across its terminals. In an embodiment, the frequency bypass circuit includes one or more capacitors.

Abstract: A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes a plurality of polygons. Each of the plurality of polygons includes at least one fragment. The fragment includes at least one texture and a w-value for the fragment. Each polygon has a plurality of vertices, a display area, and a texture space area. Each of the vertices has a vertex w-value. The at least one texture is associated with at least one MIP map. The MIP map includes a plurality of MIP map levels. The method and system include determining a selection value for each fragment of a polygon of the plurality of polygons. The selection value includes ½ multiplied by the base two logarithm of the texture area divided by the display area and divided by the product of the vertex w-values for each of the plurality of vertices. The selection value also includes 3/2 multiplied by the base two logarithm of the w-value for each of the at least one fragment.

Abstract: A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information, the particular packet information including a source address and a destination address. An egress port bitmap is determined based on a lookup in a forwarding table and it is determined if the destination address belongs to a trunk group of trunked ports. The incoming data packet is forwarded based on the egress port bitmap, when the destination address does not belong to the trunk group. When the destination address does belong to the trunk group, a particular trunked port of the trunk group is determined and the incoming data packet is forwarded thereto.

Abstract: A network switch that has a plurality of input ports that receive data packets. An external interface is connected to the plurality of input ports. The external interface externally transmits the data packets for processing, and receives the data packets after processing. A memory management unit is connected to the external interface and a plurality of output ports are connected to the memory management unit.

Abstract: Provided is a switched capacitor feedback circuit including two or more input ports configured to receive a corresponding a number of input signals and at least one output port. The output port is configured to output an adjusting signal. The input signals includes a number of primary signals and two or more reference signals that are associated with a first timing phase of operation. The adjusting signal is produced based upon a comparison between the primary signals the reference signals. Also provided is a pair of active devices having gates coupled together and structured to receive the adjusting signal. The active devices are configured to provide a gain to the adjusting signal in accordance with a predetermined gain factor, and facilitate an adjustment to the number of primary signals based upon the gain during a second timing phase of operation.