Abstract: A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

Abstract: A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

Abstract: A network switch for network communications is disclosed. The switch includes a first data port interface, supporting at least one data port transmitting and receiving data at a first data rate and a second data port interface supporting a at least one data port transmitting and receiving data at a second data rate. The switch also has a CPU interface configured to communicate with a CPU and a memory management unit for communicating data from at least one of the first and second data port interfaces and a memory. It also has a communication channel for communicating data and messaging information between the first and second data port interfaces and the memory management unit and a plurality of semiconductor-implemented lookup tables including an address resolution lookup table, a layer three IP lookup table and VLAN tables.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A telephony system and method is provided that reduces delay and provides better utilization of upstream bandwidth in delivering packet telephony services to a plurality of subscriber lines via a cable modem system. An exemplary system includes a plurality of voice processing modules, a host processor, and a buffer. Each voice processing module receives digital voice signals from a separate set of subscriber lines, compresses the digital voice signals to generate a voice packet, and transfers the voice packet to the buffer. The host processor then assembles a packet by concatenating the voice packets and transmits the assembled packet for delivery over a data network. Because the plurality of voice processing modules process the voice packets in parallel, delay is reduced in the assembly and transmission of the assembled packet.

Abstract: A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

Abstract: A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.

Abstract: Provided is a circuit to convert input CMOS level signals having a predetermined duty cycle to CML level signals having a higher duty cycle. The circuit includes two differential transistor pairs connected together. The two differential pairs are constructed and arranged to use gates of the associated transistors as inputs to receive and combine a number of phase shifted CMOS input signals. The combined CMOS input signal are converted to CML level signals which are provided as circuit outputs.

Abstract: An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum.

Abstract: A method of forwarding data in a network switch fabric is disclosed. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information including an opcode value. The opcode value allows the fabric to determine the packet type, sucha a whether the packet is a broadcast packet, a unicast packet, a multicast packet, etc. Based on the opcode value read, a particular forwarding table of a plurality forwarding tables is read and an egress port bitmap is determined based on entries read from the particular forwarding table. The incoming data packet is then forwarded based on the egress port bitmap. In addition, the architecture of the switch fabric is also disclosed.

Abstract: A memory management unit (MMU) for a network switch fabric for forwarding data is disclosed. The MMU has an ingress port interface receiving portions of a data packet and an egress port interface, connected to ingress ports of the fabric through an ingress bus ring. The MMU also includes a cell packer, that groups packet data into cells and a packet pool memory, that stores cells received from the cell packer. The MMU also includes a cell unpacker, where the cell unpacker separates stored cells before releasing the cells to an egress port. The MMU also includes an egress scheduler communicating with the cell unpacker, where the egress scheduler determines which packet data should be retrieved from the packet pool memory according to priority rules. The priority rules can be a deficit round robin scheduling algorithm or a weighted round robin scheduling algorithm.

Abstract: A network switch for network communications includes at least one data port interface supporting a plurality of data ports transmitting and receiving data. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the at least one data port interface. A memory management unit is provided for communicating data from at least one data port interface and the memory. A communication channel is provided, for communicating data and messaging information between the at least one data port interface, the memory, and the memory management unit. The configuration of the network switch also includes a fast filtering process, with the fast filtering processor filtering packets coming into the at least one data port interface. Selective filter action is taken based upon a filtering result.

Abstract: A method of handling data packets in a series of network switches includes receiving an incoming data packet at a data port of a first switch of the series of network switches. A module id bitmap of the incoming data packet is resolved and a bit corresponding to the first switch of the module id bitmap is examined to determine if the bit is set. A destination address of the incoming data packet is resolved when the corresponding bit is set and the incoming data packet is forwarded or dropped based on the destination address. When the corresponding bit is not set, the incoming data packet is forwarded to a next switch of the series of network switches. A network switch configured to allow for cascading of data packets is also disclosed.

Abstract: Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path.

Abstract: A method of handling data packets in a network switch is disclosed. The method includes placing incoming packets into an input queue and applying the input data packets to an address resolution logic engine. A lookup is performed to determine whether certain packet fields are stored in a lookup table; and the result of the lookup is also examined to determine if it provides a trunk group ID for a particular data packet of the input data packets. When the lookup provides a trunk group ID, the trunk group ID is used to determine an egress port and the particular data packet is forwarded to the egress port. Alternatively, the packet is discarded, forwarded, or modified based upon the result of the lookup, where the lookup does not provide a trunk group ID. A network switch using the method is also disclosed and methods directed to mirroring of data packets are also disclosed.

Abstract: A network switch for network communications is disclosed. The switch includes a first data port interface, supporting at least one data port transmitting and receiving data at a first data rate and a second data port interface supporting a at least one data port transmitting and receiving data at a second data rate. The switch also has a CPU interface configured to communicate with a CPU and a memory management unit for communicating data from at least one of the first and second data port interfaces and a memory. It also has a communication channel for communicating data and messaging information between the first and second data port interfaces and the memory management unit and a plurality of semiconductor-implemented lookup tables including an address resolution lookup table, a multicast table, an IP multicast table and VLAN tables.

Abstract: A network switch for network communications is disclosed. The switch includes a first data port interface supporting at least one data port transmitting and receiving data at a first data rate and a second data port interface supporting at least one data port transmitting and receiving data at a second data rate. The switch also has a CPU interface configured to communicate with a CPU and a memory management unit for communicating data from at least one of the first and second data port interfaces and a memory. It also includes a communication channel for communicating data and messaging information between the first and second data port interfaces and the memory management unit and a plurality of lookup tables, including an address resolution lookup table and a VLAN table.

Abstract: A method of handling data packets in a series of network switches is disclosed. An incoming data packet is received at a data port of a first lower capacity switch of the series of network switches and a stack tag is resolved from a header of the incoming data packet. The incoming data packet is forwarded to a first higher capacity switch, on a first stacked connection operating at a first data rate, based on the stack tag. A destination address of said incoming data packet is resolved by the first higher capacity switch and the header of the incoming packet is modified. The incoming data packet is forwarded to a second higher capacity switch, on a second stacked connection operating at a second data rate, based on the resolved destination address, where the header of the incoming data packet is modified and the incoming data packet is forwarded to a second lower capacity switch on a third stacked connection operating at the first data rate.

Abstract: A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.