Abstract: In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data.

Abstract: When a fault-on-fault condition arises in a data processing system which follows a backup fault procedure in the fault handling process, control is passed to dedicated firmware. Fault flags are reset and information vital to maintaining operating system control is sent to a reserved memory (which can be written to in limited circumstances) under firmware control. Control is then transferred to an Intercept process resident in the reserved memory which attempts to build a stable environment for the operating system to dump the system memory. If possible, a dump is taken, and a normal operating system restart is carried out. If not possible, a message with the vital fault information is issued, and a full manual restart must be taken. Even in the latter case, the fault information is available to help in determining the cause of the fault-on-fault.

Abstract: In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Each Target processor is mapped to a Host thread. When a page fault is detected by the Host operating system, it is checked to see if it belongs to the Target system, and if it does, the executing thread transfers its processor identity to a free thread, and then completes processing the page fault. Upon completion, it marks the processes that had been executing on that thread and processor as available for execution, then blocks until activated. Another thread, upon dispatching that process, wakes up the blocked thread and transfers its processor identity to that thread, which continues to execute the interrupted process.

Abstract: In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a “set gate control flag” command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.

Abstract: A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the CPU's processor when access to a given page in main memory is sought. Each entry in the associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. An incrementable multi-digit counter in the CPU stores a current validity count. When access to a data page is sought, a comparator receives: 1) the high order virtual address component of the data page; 2) the high order virtual address component read from the associative memory entry; 3) the multi-digit validity count read from the associative memory entry; and 4) the multi-digit current validity count in the counter.

Abstract: A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit incrementable validity counter. The target associative memory stores a plurality of entries in accordance with a low order virtual address component issued by the target processor when access to a given page in main memory is sought. Each entry in the target associative memory includes fields respectively holding: 1) a high order virtual address component; 2) a real page address; and 3) a multi-digit validity count. The target multi-digit counter stores a current validity count.

Abstract: Atomic multiple word writes are provided when emulating a target system that supports atomic multiple word writes on a host system that does not. For each except the last word to be written, a gate flag is read, tested, and locked when it is found unlocked. The words are then written to memory in reverse order, unlocking the gate flags as they are written. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A processor in a data processing system having multiple cache memories performs cache memory or processor module affinity dispatchin. Processes awaiting dispatch are stored in prioritized queues. Each queue has a priority chain, and a chain for each cache memory or processor module, with each chain containing processes ready for dispatch. The dispatcher checks the queues in priority order, starting with the priority chain for a queue, followed by the chain corresponding to the cache memory or processor module that the process last executed upon, followed by chains corresponding to other cache memories or processor modules.

Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

Abstract: An integrated development environment on a client provides for developing transaction programs, web pages, and applets for execution on a high performance transactional based World Wide Web server. The transaction programs are developed on the client, then automatically transferred to the server, where they are automatically compiled, linked, loaded into a TP library, registered with a TP monitor for execution, and tested. Similarly, the web pages and applets are developed on the client, then automatically transferred to the server, loaded into a database, and tested.

Abstract: A data processing system participating in two-phase transaction processing operations which, when a system failure occurs while one or more transactions are in process, can successfully rebuild “in-doubt” states even when another system failure occurs during an attempt to effect the rebuild. The system includes a file management system having exclusive access to reserved locations in the memory for reading and writing meta-data therein and physical file access logic selectively coupling the memory and the database access application, the physical file access logic incorporating file protections which are controlled by the file management system; such that, in the event of a failure, the local state of the transaction can be faithfully rebuilt after restart by accessing the meta-data.

Abstract: Disk drives are mirrored through duplication controlled by disk controllers. Each disk controller controls writing to a set of disk drives. A disk write request to one disk controller causes that disk controller to write to one of its disks and to transmit the write request to another controller that in turn writes to its disk. The second controller then acknowledges the write to the first controller, which in turn acknowledges the write to the computer issuing the request. The first controller further logs the writes in a log file. This allows efficient resynchronization after mirroring is broken and reestablished, as well as removing cable length restrictions between controllers.

Abstract: In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors (92) sharing an L2 cache (94) differs from the time it takes for those signals to travel between processors (92) not sharing the same L2 cache (94). This difference, or DELTA, is dynamically computed by computing (332) the time it takes for a invalidate cache line cache command to travel between a local processor (92) and a master processor (92). This computation (334) is then made for the time it takes the signal to travel between a remote processor (92) and the master processor (92). The difference (336) is the DELTA value in cycles. This DELTA value can then be utilized to bias delay values when exhaustively testing the interactions among multiple processors in a CC-NUMA environment (180).

Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.

Abstract: Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started from one system to execute on a second heterogeneous system. Results are then returned to the first system. Checkpointing and later restarting is also initiated from a first system for execution on the second heterogeneous system.