Abstract: In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by loading the safe store buffer from a safe store stack frame, then delaying loading registers either until actually utilized, or by a background process that loads registers utilizing unused memory cycles. A flag is used for each register that indicates whether the register contents are valid. This flag is cleared for each of the registers whenever such a state transition is made. Then, the flag is set for a register when it is referenced and made valid.

Abstract: A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe, constituting serially-coupled registers, is used to step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline.

Abstract: A method and system for facilitating the creation of warehouse requests in a data warehouse system. During the design of the data warehouse tables, a repository tool is used for storing a number of new objects such as source and target databases, source and target tables and warehouse requests that are graphically defined and linked together by an administrator with the repository tool. The resulting visual design is so drawn so as to serve as input for each warehouse request to be generated. The administrator invokes a data replication component that operatively couples to the repository tool signaling that the warehouse request is to be implemented. The data replication component automatically creates the different subcomponents of the request by accessing various links stored by the repository tool and displays a visual representation of the subcomponents and their relationships to each other to the administrator.

Abstract: A method and database organization for use by a plurality of client systems wherein a database contains a plurality of table structures for storing a product directory index and a minimum number of product related information entries utilized in generating a bill of materials document for a particular user designated customer product. The system also includes a selection menu facility component and a data selection component, both of which operatively couple to the database. The selection menu facility component enables an operator to access the product directory index for obtaining a number of key information values pertaining to a particular printed circuit board assembly.

Abstract: A configuration system and method uses a program device containing configuration software for configuring applications to be executed by a processing system through the use of externally provided values corresponding to environment variables that are used to define an execution environment for all of the applications to be executed by the system. The configuration system is used to establish a plurality of configuration file sources to be used in configuring applications wherein the files define a plurality of different operational levels. Each configuration file stores the values representative of a corresponding number of configurable items defining the environment for executing the applications. The values of each level has a pre-established override capability over the values of other levels.

Abstract: A multihomed host system is configured with independent front end processor transport providers, each having its own network protocol stack and each being connected to a different TCP/IP network or subnetwork or to different portions of the same network which in turn connects to an internetnetwork. The host system software includes a TCP/IP Transport Agent located between a sockets interface and the host system's input/output supervisor and driver facilities. The TCP/IP Transport Agent is enhanced to include a FEP Multihoming and Routing component for providing a multihoming capability. The FEP Multihoming and Routing component utilizes a plurality of components which are configured from the same administrator supplied configuration and static routing information furnished to the FEPs for configuring their respective TCP/IP stack facilities.

Abstract: A host system includes a multicache system configured within a host system's memory which has a plurality of local and central cache systems used for storing information being utilized by a plurality of processes running on the system. The central cache system includes an obsolete code management (OCM) component that operates to detect and remove obsolete entries stored within the central cache system. The OCM component operates to remove obsolete code from all the caches when events cause such obsolescence, e.g., data definition language (DDL) statements are executed. In certain situations, by being able to perform such operations during DDL statement processing, the OCM component further enhances overall system operation.

Abstract: A host system includes a multicache system configured within the host system's memory which has a plurality of local and central cache systems used for storing information being utilized by a plurality of processes running on the system. Persistent shared memory is used to store control structure information entries required for operating central cache systems for substantially long periods of time in conjunction with the local caches established for the processes. Such entries includes a descriptor value for identifying a directory control structure and individual sets of descriptors for identifying a group of control structures defining those components required for operating the configured central cache systems. The cache directory structure is used for defining the name of each configured central cache system and for providing an index value identifying the particular set of descriptors associated therewith.

Abstract: The main storage of a system includes a virtual memory space containing a plurality of virtual frame buffers for storing information transferred from disk storage shared by a number of virtual processes being executed by the system. An associated buffer table and aging mechanism includes a buffer table storing a plurality of buffer table entries associated with the corresponding number of virtual buffers used for controlling access thereto and an age table containing entries associated with the buffer table entries containing forward and backward age pointers linked together defining the relative aging of the virtual frame buffers from the most recently used to least recently used. Each buffer table entry has a frequency reference counter which maintains a reference count defining the number of times that its associated virtual buffer has been uniquely accessed by the virtual processes.

Abstract: A mapping between terminal presentation and a Graphical User Interface to an end user using a web browser is provided. The mapping representation is created to support a selected screen image sent from the application to the web browser. A generic interpretative applet and the screen mapping representation is forwarded to a web server and in turn is downloaded to a web browser using a well known protocol. The applet generates and processes messages in an acceptable presentation, e.g. IBM 3270 format, and exchanges those messages directly with a receiving application across a computer network, thereby reducing or eliminating message translation and traffic through intermediate applications and systems.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed.

Abstract: Each processor (92) in a data processing system (80) caches a copy of the master calendar clock (97). The master calendar clock (97) and all of the cached calendar clocks (272) are periodically incremented utilizing a common clock (99). Whenever a processor (92) in the system (80) loads the master calendar clock (97) with a new value, that processor (92) broadcasts a cached calendar clock updated interrupt signal (276) to all of the processors in the system. In response to this interrupt (278), each processor (92) clears its cached calendar clock valid flag (274). Whenever a read calendar clock instruction is executed on a processor (92), the flag (274) is tested, and if set, its cached calendar clock (272) value is returned. Otherwise, the master calendar clock (97) value is retrieved, written to that processor's cached calendar clock (272), and returned. The cached calendar clock valid flag (274) is set to indicate a valid cached calendar clock (272).

Abstract: A search mechanism improves the performance of a queue system including a queue for storing a plurality of data items and search mechanism by maintaining a key cache data structure having an array of entries, each of which have a key field and a pointer field. The key and pointer fields respectively of each cache entry are used for storing a key value of a different one of the enqueued data items of the queue and a pointer to that enqueued item. The key of each data item to be enqueued is used to generate an index value for accessing a location of the key cache array to obtain immediate access to the corresponding enqueued data item thereby reducing the search time for determining the proper point within the queue for inserting the data item to be added.

Abstract: In order to gather, store temporarily and efficiently deliver safestore information in a CPU having data manipulation circuitry including a register bank, first and second serially oriented safestore buffers are employed. At suitable times during the processing of information, a copy of the instantaneous contents of the register bank is transferred into the first safestore buffer. After a brief delay, a copy of the first safestore buffer is transferred into the second safestore buffer. If a call for a domain change (which might include a process change or a fault) is sensed, a safestore frame is sent to cache, and the first safestore buffer is loaded from he second safestore buffer rather than from the register bank.

Abstract: A computer system includes a main processor and a supervisory processor. The main processor provides status signals when a fault condition exists and responds to control signals for fault recovery. The supervisory processor instantiates objects from a fault class in response to the status signals. Objects are polymorphic in that each object has substantially the same methods available at its interface though each object corresponds to a different fault. Methods accomplish fault recovery by providing the control signals. System operation exhibits fewer errors by the supervisory processor and system expansion is more easily accommodated with greater reuse of proven program code than possible with prior supervisory processor software.

Abstract: The emulation of a first system disk drive on a second processing system including a second system user level process including first system user and executive tasks issuing disk input/output requests. An emulator level is interposed between the second system user level process and a kernel level and includes a pseudo device driver corresponding to the first system disk drive and the kernel level includes a kernel process corresponding to the pseudo device driver and emulating the disk drive. The pseudo device driver and the kernel process execute in a second system process to emulate the operations of the disk drive and the kernel process emulating the disk drive is a file input/output process. The pseudo device driver includes a pseudo device queue, a return queue and a queue manager responsive to first system disk input/output instructions and to completed disk operations.

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

Abstract: In a coprocessor which processes operands and issues a result word which may include overflow, result and truncation fields and which normally sets a truncation indicator if truncation is employed, the setting of the truncation indicator is inhibited under certain conditions to facilitate later handling of the result. Determinations are made as to whether the result and truncation fields of the result word are zero and as to whether the overflow field is non-zero. If the result and truncation fields are zero, the setting of the truncation indicator is inhibited notwithstanding a non-zero value in the overflow field. Break point position information is processed to obtain masks of bits having logic "1" values for testing the result and truncation fields and logic "0" values for testing the overflow field, the masks then being logically ANDed with the result word. If the result of the ANDing process is a logic "0", the truncation indicator is inhibited from being set.

Abstract: A method allowing the gradual deployment of a new security policy on a data processing system wherein users may access certain objects under the former authorization until complete security implementation is achieved. A user having a security profile satisfying the former security policy criteria, but not the new security criteria, would normally be denied access to objects that were formerly accessible. With the present invention, an intermediate security profile is created while the new policy is being implemented wherein such a user's access is not granted, but not necessarily denied. This tertiary state is achieved by supplementing the security profile of the user to satisfy the new security criteria. When a user attempts object access providing an identity token valid under the former system, arbitration occurs which may result in the synthesis or substitution of a proxy identity which is compliant with the new policy.

Abstract: An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device.