Abstract: When a fault-on-fault condition arises in a data processing system which follows a backup fault procedure in the fault handling process, control is passed to dedicated firmware. Fault flags are reset and information vital to maintaining operating system control is sent to a reserved memory (which can be written to in limited circumstances) under firmware control. Control is then transferred to an Intercept process resident in the reserved memory which attempts to build a stable environment for the operating system to dump the system memory. If possible, a dump is taken, and a normal operating system restart is carried out. If not possible, a message with the vital fault information is issued, and a full manual restart must be taken. Even in the latter case, the fault information is available to help in determining the cause of the fault-on-fault.

Abstract: In a data processing system with multiple processors, failing processors are replaced with spare processors. This allows the system to continue to operate without degradation. An intercept process is notified of a processor failure so that it can collect processor registers and states. If the registers and states are collected correctly, an indication is set that relief is possible. The intercept process notifies a service processor of the failure and then halts the failed processor. The service processor then notifies the operating system of the failure and that relief is possible. If fast relief is acceptable, a spare processor is initialized and resumes execution with the state and registers of the failed processor. A service processor modeling file controls the number of active and spare processors in a system. Spare processors sharing the same L2 cache with the failed processor are preferred as replacements.

Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.

Abstract: A processor (92) contains a Trace RAM (210) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller (256) and the arithmetic (AX) processor (260). A second trace mode selectively traces full operand words that result from microcode instruction (242). Each microcode instruction word (242) has a trace enable bit (244) that when enabled causes the results of that microcode instruction (242) to be recorded in the Trace RAM (210).

Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.

Abstract: In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This “unfair” memory access to the desired spin gate can result in starvation of processors from other CPU modules. This problem is solved by “balking” or delaying a specified period of time before attempting to close a spin gate whenever either one of the processors in the same CPU module just opened the desired spin gate, or when a processor in another CPU module is spinning trying to close the spin gate. Each processor detects when it is spinning on a spin gate. It then transmits that information to the processors in other CPU modules, allowing them to balk when opening spin gates.

Abstract: In order to maintain consistent file systems for disaster recovery purposes between two computer systems, the file names from a first computer system are copied into a first database and the file names from a second computer system are copied into a second database. The file names in the two databases are then compared for duplicates. Based on a switch, a list of either duplicated or unduplicated file names is generated. The file names in the generated list are filtered, if desired, and then displayed. A user then has the ability to review the list of generated file names and select some or all of them for duplication or deletion, as required.

Abstract: In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, determining a working space base address for that working space, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address.

Abstract: A mass memory storage unit includes a cabinet and one or more drawers incorporated into the cabinet. Each drawer is movable between closed and open positions to permit access to the interior for service. Inside each drawer, there is a connector plane disposed generally to one side of the drawer interior and parallel to the direction of travel between the closed and open positions. The connector plane incorporates connectors for receiving storage devices (for example, hard disk drives), each incorporating a connector which detachably mates with one of the connectors on the connector plane. Support and interface devices are coupled to the connector plane by suitable complementary connectors. It is useful to provide a cable, which itself may be detachable from the connector plane, to establish a redundant connection such that the devices in a drawer remain in-circuit when that drawer is opened for access to the enclosed components.

Abstract: In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies whether the Target instruction has been translated into Host code, and if already translated, whether it is an entry point, middle, or last instruction in a block of code. When an emulator encounters a code tag indicating an entry point into a block of code, execution control is transferred to the corresponding Host code. Upon completion of the Host code block, execution control is returned to the emulator, with an indication of the next Target system instruction to execute. One code tag value is utilized to identify self-modified code. Another code tag value is utilized to indicate how often untranslated Target instructions have been interpreted in order to determine when to perform DOCT.

Abstract: A method of addressing mass storage memory in which information is stored in Space Control Pages of physically contiguous disk segments subject to irregularities in the mapping is disclosed. Space Control Pages fall at regular intervals across the address space. An efficient hashing method is disclosed that first hashes record keys across the entire address space to form a hash index. If the hash index falls into one of the Space Control Pages, the key is rehashed across the contiguous hash space following the Space. Control Page utilizing a second hash function. The result of the second hash function is added to the start of the contiguous hash space following the Space Control Page to generate the hash index utilized for those records that initially hashed into a Space Control Page. In all cases the generated hash index is utilized to store and retrieve records in a database or hash file.

Abstract: When emulating a Target architecture on a Host system having a different architecture, virtual to real address translation is typically expensive in terms of computer cycles. The cost can be significantly reduced by utilizing direct page table pointers to short-circuit the address translation. In a system additionally supporting segments framing portions of virtual memory, the direct page table pointers are associated with segment registers and point to the page table entry corresponding to the first location in a segment. Direct page table pointers are invalidated when underlying virtual memory management tables are modified.

Abstract: In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real address translation of a Target system effective address to a Host system virtual addresses is performed by identifying a working space for the effective address, selecting a working space base address data structure entry utilizing the corresponding working space number, determining a working space base address from that selected working space base address data structure entry, and then performing a linear translation multiplying the effective address by a constant and adding it to the working space base address to generate the host system virtual address. A corresponding working space limit entry can be utilized to bounds check the addresses generated.

Abstract: A cache manager of a relational database management system (RDBMS) is able to bypass time consuming search operations through the use of a key memory structure and locate generated code segments within an SQL cache within a minimum of time. The SQL cache contains the generated code segments used to execute SQL statements as well as the structures and program logic used for maintaining the cache. The key memory structure is located in an area of memory utilized by the SQL runtime routines in executing applications. The runtime routines provide an interface between the application and the RDBMS.

Abstract: A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe is used to selectively step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline.

Abstract: A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits.

Abstract: A system and method that enhances the data access performance of a multi-layer relational database manager by expanding the code generation component layer of the database manager to include a number of performance enhancing subroutines designed to execute functions performed by lower component layers substantially faster than if the functions were executed by such lower component layers. Each such subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the processing of a SQL request. During process of generating code for a specific SQL query, the code generation component layer inserts calls to the different performance enhancing subroutines in place of normally included calls to lower component layers. This results in the insertion of the different performance enhancing subroutines into the generated code.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an entry descriptor. The entry descriptor is verified and if valid, is utilized to setup the environment for the appropriate fault handling routine and to enter such. The fault array pointer table is located in a reserved memory that cannot be overwritten by I/O. During the boot process, the fault array pointer table entries, along with a fault-on-fault pointer are updated to point at entry descriptors stored in the reserved memory. Additionally, the fault-on-fault entry descriptor that rebuilds the processor environment if necessary from information in reserved memory.

Abstract: A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lock. Memory and bus traffic are minimized during this waiting by first reading and testing the memory location. Then, the memory location is not read and tested again until the local copy of the cache line containing that memory location is invalidated by another processor. This feature is utilized both for a Lock instruction and a Wait for Change instruction, both of which utilize a timer parameter for specifying a maximum number of cycles to wait for another processor to modify the specified location in memory.