Abstract: Atomic multiple word writes are provided when emulating a target system that supports atomic multiple word writes on a host system that does not. For each except the last word to be written, a gate flag is read, tested, and locked when it is found unlocked. The words are then written to memory in reverse order, unlocking the gate flags as they are written. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

Abstract: Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found unlocked. Check speculation instructions are utilized after the gate flag tests to verify that the corresponding cache lines have not been invalidated through a write by another processor since the speculative loads were issued. In a host system with a longer word size than the target system, the gate flags can be stored in otherwise unused bits in the host system words containing the target system words to be written.

Abstract: A dispatcher in a multiprogramming or multitasking operating system in a data processing system selects the next task to be executed by an available processor. Access to shared resources are controlled by locks and queues, where tasks are queued when they find the shared resource locked, and dequeued one by one as the lock is unlocked. When a lock is unlocked, the first task in a FIFO queue is dispatched with a temporary priority at least as high as any in the queue. This first task must retain this temporary urgency until it releases the resource or until its urgency is further increased due to the addition of a higher priority task to the resource queue or a dependent resource queue. This prevents starvation of higher priority tasks waiting in the FIFO queue.

Abstract: Disk drives are mirrored through duplication controlled by disk controllers. Each disk controller controls writing to a set of disk drives. A disk write request to one disk controller causes that disk controller to write to one of its disks and to transmit the write request to another controller that in turn writes to its disk. The second controller then acknowledges the write to the first controller, which in turn acknowledges the write to the computer issuing the request. The first controller further logs the writes in a log file. This allows efficient resynchronization after mirroring is broken and reestablished, as well as removing cable length restrictions between controllers.

Abstract: A client system utilizes a standard browser component and a transaction protocol gateway (TPG) component that operatively couples to the standard browser component. The browser component initiates the utilization of new session connections and reuse of existing session connections as a function of the coding of the universal resource locators (URLs) contained in each issued request. Each URL is passed to the TPG component that examines a context field included within the URL. If the context field has been set to a first value, the TPG component opens a new session connection to the server system and records the session connection information in a persistent session table (PST) component maintained by the TPG component. If the context field has been set to a second value, then the TPG component obtains the session connection information in the PST component for the established session connection and passes the data from the browser component to the server system over the existing persistent session connection.

Abstract: In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by utilizing a plurality of sets of registers maintained in a round-robin system. Whenever a transition is made to a higher security environment, a switch is made to a different set of registers. Then, when a transition is made back to the lower security environment, a switch is made back to the previous set of registers. Writes to memory copies of registers are detected, and only those registers whose memory copies have been modified are restored from the memory copy.

Abstract: An Application Programming Interface (API) provides interoperability between different monitoring and administrative components of a data warehouse system that utilizes different standard protocols. One of the protocols is the well known data connectivity protocol, Open Database Connectivity (ODBC) that defines a standard interface between applications and data sources. A second one of the protocols is the well known network management protocol, Simple Network Management Protocol (SNMP) that defines a standard interface between an agent component and a network management system. The API provides a facility that enables the different components to access user and connection information maintained by an ODBC server component derived from servicing client system application SQL queries made by system users.

Abstract: In the emulation of a target system utilizing a multiprocessor (12) host system (10) with a longer word length than the target system, processor, memory, and cache overhead are minimized by utilizing a locked compare-exchange to update fill words in memory. The old contents of a word (48) in memory are loaded (80) into a first register (52). A loop is then entered. The contents of the first register (52) are copied (82) into a second (54). The contents of the second register (54) are then appropriately modified (84), depending on the instruction being emulated. After a lock (90), the two registers are compare-exchanged (86) with the memory word (48), resulting in the modified second register (54) being written to the memory word (48) if the contents of the first register (52) match. Otherwise, the compare-exchange instruction (86) loads the current copy of the word (48) into the first register (52), and the loop repeats.

Abstract: A database management optimizer detects patterns in SQL that occur when search conditions are present that represent ranges of values across multiple columns of a table. These patterns are recognized and translated into simpler key value ranges that can be used to provide more efficient use of database indexes.

Abstract: A system and method that enhances the index processing performance of a multi-layer relational database manager by expanding the code generation component layer of the database manager to include an index processing performance enhancing subroutine designed to execute functions performed by lower component layers substantially faster than if the functions were executed by such lower component layers. The subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the execution of a SQL request. The output code generated to execute a specific SQL query, including calls to the index processing subroutine in place of normally included calls to the lower component layer. This enables the generated code to perform lower component layer functions with specialized code designed to increase performance.

Abstract: A system and method that enhances the row retrieval performance of a multi-layer relational database manager by including in the code generation component layer of the database manager a row retrieval performance enhancing subroutine designed to execute functions performed by a lower component layer substantially faster than if the functions were executed by such lower component layer. The subroutine includes logic for establishing the conditions under which the particular subroutine is invoked during the execution of a SQL request. The output code generated to execute a specific SQL query, including calls to the row retrieval subroutine in place of normally included calls to the lower component layer. This enables the generated code to perform lower component layer functions with specialized code designed to increase performance based on the characteristics of the data being retrieved.

Abstract: A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.

Abstract: When emulating a Target architecture on a Host system having a different architecture, virtual-to-real address translation is typically expensive in terms of computer cycles. The cost for translating addresses for instruction fetches can be significantly reduced by maintaining both a virtual and a real memory address instruction counter. Both are incremented on each instruction fetch. Virtual to real address translation is eliminated as long as execution continues on the same real memory page of instructions. Alternatively, only a real memory address instruction counter is incremented, while maintaining a delta instruction counter value to efficiently translate back and forth to and from the corresponding virtual memory address.

Abstract: A client system utilizes a standard browser component and a transaction protocol gateway (TPG) component that operatively couples to the standard browser component. The browser component initiates the utilization of new session connections and reuse of existing session connections through the use of session pools as a function of the coding of the universal resource locators (URLs) contained in each issued request. The gateway component builds a plurality of session pool table structures at client system startup that define an initial number of pre-established persistent session connections for enabling communication with a number of server systems. Each browser URL is passed to the TPG component that examines a context field within the URL. If the context field has been set to a predetermined value, the TPG component in lieu of opening a new session connection to the designated server system, obtains a pre-established session connection from a session pool.

Abstract: In order to obtain mixed and space efficient use of mass memory units having different form factors into a single package, a specially configured connector plane module is provided. The connector plane module includes three identical, aligned, connector plane connectors arranged in a new configuration. Two spaced apart connector plane connectors are disposed in the same orientation with one another; but the third connector plane connector is spaced apart from and disposed in 180° orientation with respect to the second connector. With this configurtion, two mass memory storage units having a first form factor or three mass memory storage units of a second, smaller, form factor may be coupled to the connector plane to occupy substantially the same space, one mass memory unit in each case being oriented at 180° with respect to the one or two other mass memory units.

Abstract: A data communications system for supporting World Wide Web (WWW) database queries to enterprise level databases utilizes two server based programs. A first program retrieves and transmits a specified version of a specified form to an intermediate forms program. The second program has two modes of operation. In either mode, database queries to the enterprise level database are performed and results transmitted. However, in a first, standard, mode of operation, a specific version of a specific form is read from a forms database and transmitted to the requester along with the query response. In the second mode of operation, only the database query results are transmitted, along with a modified header that specifies the appropriate form. The corresponding forms are retrieved from a local forms database and merged with the query response before being displayed by a Web browser. Missing forms are requested from the Web forms program and cached for subsequent requests.

Abstract: Interactions among multiple processors (92) are exhaustively tested. A master processor (92) retrieves test information for a set of tests from a test table (148). It then enters a series of embedded loops, with one loop for each of the tested processors (92). A cycle delay count for each of the tested processors (92) is incremented (152, 162, 172) through a range specified in the test table entry. For each combination of cycle delay count loop indices, a single test is executed (176). In each such test (176), the master processor (92) sets up (182) each of the other processors (92) being tested. This setup (182) specifies the delay count and the code for that processor (92) to execute. When each processor (92) is setup (182), it waits (192) for a synchronize interrupt (278). When all processors (92) have been setup (182), the master processor (92) issues (191) the synchronize interrupt signal (276). Each processor (92) then starts traces (193) and delays (194) the specified number of cycles.

Abstract: Instrumentation statistics are tallied at the procedure level in instrumentation stack frames corresponding to subroutine stack frames. Elapsed CPU time for each entry into a procedure is computed and accumulated into a statistics table corresponding to that procedure. Also accumulated into that statistics table are the accumulated elapsed execution times of the subroutines called by this procedure. These values are initially accumulated into the instrumentation stack frame for each subroutine's parent upon subroutine exit, and then accumulated into the statistics table upon subroutine exit of the parent. Elapsed CPU time is computed by subtracting CPU time of last dispatch from the current hardware clock, then adding this to an accumulated CPU time at the time of dispatch.

Abstract: A data processing system contains a processor supporting instructions and operands utilizing a Narrow word size. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. The translation between Narrow and Wide word sizes can be either at a byte/Unicode level, or at a word level.

Abstract: Two instructions are provided to synchronize multiple processors (92) in a data processing system (80). A Transmit Sync instruction (TSYNC) transmits a synchronize processor interrupt (276) to all of the active processors (92) in the system (80). Processors (92) wait for receipt of the synchronize signal (278) by executing a Wait for Sync (WSYNC) instruction. Each of the processors waiting for such a signal (278) is activated at the next clock cycle after receipt of the interrupt signal (278). An optional timeout value is provided to protect against hanging a waiting processor (92) that misses the interrupt (278). Whenever the WSYNC instruction is activated by receipt of the interrupt (278), a trace is started to trace a fixed number of events to an internal Trace Cache (58).