Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.

Abstract: Allocation information for a random access memory is stored in a separate memory or memory area. Each memory block in the RAM is divided into 2.sup.n equal-sized spaces, and a memory allocation tree structure is established which stores, in a separate random access memory (which can be a dedicated, non-allocable section of the first random access memory), a single space availability indicator at a first level representing 2.sup.n equal-sized spaces, a pair of pair of space availability indicators at a second level each representing 2.sup.n-1 equal-sized spaces, and so on until a plurality of space availability indicators are placed at a suitable lower level tree structure such that each represents a single equal-sized space. When a request for allocation of memory space is made, the allocation information for a memory block is checked to determine if a space availability indicator at the level which could accommodate the request is set to the first value. (If not, a different memory block is checked.

Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a safestore memory for storing the contents of the plurality of software visible registers, after a data manipulation operation, is provided. Iterative execution instructions subject to a page fault are specially handled in that, during execution, status information indicative of the ongoing status and valid intermediate results are additionally stored in the safestore memory. Then, in the event of a page fault encountered during the execution of the iterative execution instruction, execution is suspended until access to a valid copy of the missing page is obtained. When a valid copy becomes available, the execution of the iterative execution instruction is restarted at the point at which the valid intermediate results had been obtained prior to occurrence of the page fault.

Abstract: The present invention which makes use of knowledge developed at the program writing stage by the programmer or by software tools such as a compiler that some substantial number of data accesses would miss in the cache hierarchy to the detriment of performance and that it would be possible to prefetch the necessary data in parallel with performing useful work. The invention provides a background memory move (BMM) mechanism by which the program can specify such prefetching of data from main memory to a quickly-accessible data cache and by which the program can determine which such prefetches have completed. This mechanism makes it possible to improve the performance of the computer system through the effective use of added concurrency while avoiding the overheads of process-swapping.

Abstract: In order to reduce the size of the memory employed to store firmware, the firmware is written in virtual control words which are then reduced by allotting them to a primary control word memory and at least one secondary control word memory which is addressed by a field in the primary control word memory. A virtual set of secondary control words are each divided into a plurality of fields, and each field of each secondary virtual control word is marked as guarded or "don't care". If a field is marked as "don't care", the function represented by the virtual control word will perform properly no matter what the content of that field. Virtual control word pairs are then examined to ascertain if they can be combined into a single control word.

Abstract: A method and apparatus provides an analog mode of operation of a standard test access bus interface based on a standard boundary scan architecture which is limited to use of digital signals. Circuits are included in the interface which enable the sharing of control paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.

Abstract: A fault handling process in a computer system subject to CPU design errors and functioning under an operating system (OS) having an integral fault handling module includes the steps of: setting an intercept flag when a central processor fault occurs if the fault is to be directed to a preprocessor; establishing a safestore frame which includes information identifying the type of fault and whether the intercept flag is set; and transferring control to the OS fault handling module; then in the OS fault handling module, determining whether the intercept flag is set; if the intercept flag is not set, handling the fault in the OS fault module; if the intercept flag is set, transferring control from the OS fault module to an Intercept Process written in machine language; and handling the fault in the Intercept Process.

Abstract: A method executed by a computer system for providing a visual interface Nor specifying relationships and correspondences between two graphically displayed database schemas in object oriented form. After displaying two schemas, selecting an object one from each and displaying their attributes. After selecting a pair of attributes if they are key attributes, comparing their domains and recording same and checking to determine if there is a mis-match as to data types. If either attribute is not a key attribute, checking to see if there is a mis- match of data types. If in either case there is no mismatch, then select a name for the combined attribute and deleting the attributes so combined from the list of attributes for each object. Repeating until all attributes of all objects of the two schemas have been combined, then generating a file containing all correspondences and a list of all assertions of correspondences.

Abstract: In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a interprocessor command or instruction identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group.

Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.

Abstract: A method for integrating the schemas of a plurality of independent and heterogeneous database management systems of a distributed database management system (DDBMS). The DDBMS includes a computer system in which the DDBMS resides and one or more subservient computer systems. The schemas of two of the independent database systems are fetched from the subservient computer systems. The schemas are converted from a relational database form to an object-oriented form. The schemas are then normalized and displayed graphically. Equivalencies are identified and the two schemas are integrated. These steps are repeated until the schemas of all data bases to be integrated have been integrated into a single integrated, or global schema.

Abstract: An ESD protection system which shields PCAs during the assembly process comprises transportable support means for holding an ESD bag in a predetermined position which is convenient both for the insertion and extraction of a PCA(s) and for observing stored PCA(s), thus ensuring proper handling. The system has first and second attachment means for attaching the ESD bag to the frame and for holding papers associated with the PCA(s) outside the ESD bag and for providing the weight necessary for maintaining a sealing fold in the bag whenever the PCA(s) are enclosed therein. The transportable support means is a frame which is constructed to mate with a rack designed for accommodating a plurality of frames. When so mated, the rack provides the desired level of stability and orderly positioning of a desired number of frames spaced apart such that the ESD bags attached to the frames may be easily observed for correct loading, closure and paperwork processing.

Abstract: A database system provides a manufacturing factory environment which integrates a plurality of manufacturing processes used to control the manufacture of a number of electronic board products on a plurality of manufacturing lines. The database system responds to operator initiated commands and provides a predetermined number of control table structures in memory for storing predetermined types of control parameter entries used in controlling the manufacturing processes. The database system includes a number of control mechanisms which in response to operator commands perform sequences of operation for enabling process steps to be added, applied or linked to other processes or modified in a reliable and efficient manner.

Abstract: A method for graphically displaying an object-oriented schema on the screen of a computer system. The input is an object-oriented schema of a database in textual form. The input is parsed to identify the components of the schema. A connectivity matrix is developed in order to determine the number of interrelationships of objects. The screen is partitioned into cells, with each cell designed to hold an object and its attributes, with the object that has the maximum number of relationships with other objects being placed in the center cell of the grid, and related objects in adjacent (surrounding) cells. Relationships between objects and their attributes are identified by lines, arcs, labels, and arrows drawn on the screens of the display device of the computer system. The user can interface with the system by clicking on the graphical objects appearing on the computer screen.

Abstract: A method for improving the efficiency of queries in relational database management systems that use the exhaustive method of query optimization. The join structure of the query is examined prior to query optimization and tables are ordered according to graph theory. The tables in the FROM clause of the query are then reordered before query optimization. The access plan is thus developed from an already near-optimal table ordering. As a result, the number of table permutations examined during query optimization is pruned, the time to examining large numbers of table order permutations is avoided, and the optimization cost is reduced.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. When the two systems are split, each system is controlled by the clock and definer signals generated by its own CGD unit. When the two systems are merged, one CGD unit is designated as master, and its clock and definer signals drives both sides of the redundant system. Special logic included in each CGD unit ensures that the change from master to slave (or slave to master) operation is performed without error. This special logic includes circuitry which places a temporary hold at a predetermined logic level on the local clock and definer signals, which are in use when the switch is made, when the local clock and definer signals are both at the predetermined logic level.

Abstract: A software implemented control mechanism is used in a test system for assigning unique pre-established electronic addresses which are to be written into the memory elements of printed circuit boards during the manufacture thereof. Each PCB is previously encoded with a scannable board serial number label, and the test system includes a processing unit and a memory configured for storing test software for testing PCBs. The control mechanism is incorporated into the test software which when installed into the test system configures the system's memory for assigning electronic addresses. The control mechanism includes first and second sets of tables containing entries which define the ranges of valid serial numbers and preallocated electronic addresses.

Abstract: A reconfigurable computer system which includes two computer subsystems, corresponding lines of the system busses of the two computer subsystems being interconnected by solid state switches. Each of the computer subsystems includes a control component, a service processor, which when an error is detected that would render the subsystem inoperative, causes the solid state switches to open to sever the connection between the system busses of the two computer subsystems so that the computer subsystem that has not suffered such a failure can continue to operate. A communication link is also established between the two service processors. Either, or both, service processors can sever the link between them.

Abstract: A local host data processing system operating under the control of a local host operating system includes components of multiple emulating hosted operating systems. The host operating system further include a TCP/IP network protocol stack which couples to the communications facilities of the host system connected to a local area network for communicating with a number of remote host systems. Host and hosted operating systems share the same TCP/IP network protocol stack. A virtual network mechanism is configured within the local host system to be operatively coupled to the host network protocol stack and provide access to well-known port application programs. When so configured, the mechanism functions as another LAN to which multiple virtual host systems are attached for executing applications under control of the emulating hosted operating systems.

Abstract: A host data processing system operating under the control of a host operating system such as an enhanced version of the UNIX operating system on a RISC based hardware platform includes an emulator which runs as an application process for executing emulated system (ES) user application programs. The emulator includes a number of emulated system executive service components including a socket command handler unit and a socket library component operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server components operating in host memory. The host operating system further includes a host socket library interface layer (API) which operatively connects through a TCP/IP network protocol stack to the communications facilities of the hardware platform. The socket server components operatively connect ES TCP/IP application programs to the socket library interface layer of the host operating system when such application programs issue standard ES socket library calls.