Abstract: In order to increase the information exchange speed among the several transaction members or subsystems organized around a bus carried on a backpanel, all lines of the bus are isolated, using CMOS switches, from the stub to each transaction member which is not instantaneously required for information exchange. The CMOS switches are physically placed as close as practical to the junction of each individual stub to the bus proper. This is achieved by placing the integrated circuits containing the CMOS switches on each subsystem circuit board proximate the male-edge-connector-to-female-edge-connector regions at which the junctions between the bus proper and the stubs are established. Preferably, the CMOS switch integrated circuits are emplaced on the backpanel itself proximate the edge connector regions communicating with each of the subsystems.

Abstract: A method for addressing mass memory in which information is stored in control intervals of physically contiguous disk segments subject to irregularities in the mapping is disclosed. Such irregularities may include discontinuities at some regular interval, which may or may not be 2", and/or offset from zero with respect to a virtual address employed by a user. Within the method, a unique hashing algorithm is employed to convert a virtual address to a physical address taking into account such irregularities in the mapping. This algorithm is particularly characterized by its use of integer binary arithmetic which results in high speed and complete accuracy. For the special and common condition in which discontinuities appearing at some regular interval of 2", a similar disclosed algorithm may be employed to achieve even greater speed of address transformation.

Abstract: A session mirroring facility is utilized in conjunction with the operating system of a host system. The facility captures user input and system output in a way which is transparent to the user whose session is being captured. It can operate in selectable operating modes which allows the monitoring of a session by any number of parties as it is taking place and being recorded and the playing back of the session at some later time by one or more parties.

Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler and file management components are extended to accommodate and to to allow creation and access to linked files within both host and emulated system files.

Abstract: Method and apparatus to reduce the number of control words stored in a read only control store of a microprogrammed unit of the CPU of a large scale computer. A set of control fields are required to control the active elements of the unit to cause the unit to execute a large number of different basic operations. Typically the required set of control fields are included in control words stored in a control store controlling the unit during the execution of a basic operation. Obtaining some of the set of required control fields from other sources available within the unit results in a significant reduction in the number of control words stored in the control store without reducing the functionality of the unit.

Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler and file management components are extended to accommodate dual decor copy command which invokes the file management component to copy files in either direction between the host system and emulated system.

Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.

Abstract: In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected.

Abstract: A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred.

Abstract: A memory translation mechanism and method executing in a second system to perform first system memory operations for first system executive and user tasks executing on the second system which includes a second system memory organized as a plurality of memory segments, wherein first memory segments are designated to correspond to system memory areas and second memory segments are designated to correspond to user memory areas, and wherein each memory segment corresponds to a combination of a type of first system task and a type of a first system memory area. An interpreter maps by reading an identification of the type of the task corresponding to the first system virtual address from the task type memory and the area type value from the first system virtual address and determining a memory segment corresponding to the type of the first system task and the type of first system area referenced by the first system virtual address.

Abstract: In a central processor incorporating at least one co-processor, such as a floating point arithmetic co-processor, in addition to a basic arithmetic logic unit, the problem of rationalizing the contents of the accumulator and supplementary accumulator registers without the burden of speed penalties is addressed and solved. This is achieved by providing input/output access to a common register file and by switching control of the register file to the proper processing unit appropriately. A single, shared accumulator register and a single, shared supplementary accumulator register are included in the stack along with other sharable registers such as address modification registers. Thus, the contents of the accumulator register and the supplementary accumulator register are always up-to-date and available to all processing units in the central processor without the need for first carrying out rationalization steps.

Abstract: A distributed system includes a non-distributed computing environment (DCE) computer system and at least one DCE computer system which are loosely coupled together through a communications network operating with a standard communications protocol. The non-DCE and DCE computer systems operate under the control of proprietary and UNIX based operating systems respectively. The non-DCE computer system further includes application client software for providing access to distributed DCE service components via a remote procedure call (RPC) mechanism obtained through application server software included on the DCE computer system.

Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units or integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit for receiving data manipulation results from both BPUs and for transferring specified information words simultaneously to both BPUs upon request. These operations are controlled by cache interface control signals identically generated in each BPU. In each BPU, the control signals are arranged into first and second groups which are nominally identical. The first control signal group is transmitted to the cache unit from one BPU while the second control group is transmitted to the cache unit from the other BPU. In each BPU, parity is generated for each control group separately.

Abstract: For a data processing system which employs a cache memory, the disclosure includes both a method for lowering the cache miss ratio for requested operands and an example of special purpose apparatus for practicing the method. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same, indicating a pattern which yields information which can be combined with an address in the stack to develop a predictive address.

Abstract: An application memory card system includes a secure memory card which can be operatively connected to communicate with a host mainframe microprocessor or hand held device host microprocessor via a standard interface. The secure memory card contains an application processor and an access control microprocessor (ACP), each of which connect through an internal bus to a number of non-volatile addressable memory chips, each organized into a plurality of blocks. Each microprocessor has an additional control signal line included in a control bus portion of its bus for specifying "Execute" access. An access discrimination logic unit which connects to the internal bus and to the non-volatile memory includes an access by type memory writable by the application processor under the control of the ACP for maintaining security. The access discrimination logic unit combines the "Execute" control access signal from a microprocessor with a signal designating the microprocessor source (e.g.

Abstract: A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus.

Abstract: A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period.

Abstract: A hybrid system environment includes a proprietary operating system and processing unit and a non-proprietary operating system (UNIX based) and processing unit. The systems tightly couple to a system bus in common with a main memory and a number of multiline communications controllers and communicate through a common area of main memory. The UNIX terminal connections to such controllers are virtual connections applied by a virtual terminal driver through the system proprietary communications software components. These components include a server, a network terminal driver (NTD) and a number of multiplexer driver modules. A multiplexer physical terminal driver is included in the UNIX-based operating system and a switching mechanism is incorporated into the virtual terminal driver for enabling switching to such physical terminal driver when a user switches via a switch command to the UNIX-based operating system.

Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.

Abstract: A method and apparatus provides improved modes of operation of a standard test bus based on a standard boundary scan architecture which minimizes the number of bits required to be serially scanned into the controllers of the various devices connected to the bus by temporarily disabling scan paths not required to be utilized. Means for continuously verifying the inoperative state of test logic and for diagnosing test logic faults are also described.