Patents Assigned to Bull HN Information Systems Inc.
  • Patent number: 5696969
    Abstract: Convoys resulting from competing requests for a popular service are detected and dispersed by a scheduling procedure. When a request first enters the procedure, a determination is made as to whether the procedure is currently in the convoy disperse mode. If not, availability of the service is checked, and if it is available, the request is serviced. If the service is not available, a delay is instituted, and availability of the service is checked again. If it is still not available, a wait-for-service count is checked to determine if it exceeds a predetermined value. If not, the present request is sent to a queued wait. If so, the convoy disperse flag is set true, and the request is sent to the queued wait. If the convoy disperse flag was already true when the request was received into the procedure, a different path is taken in which a loop is entered which involves temporarily relinquishing the processor.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: December 9, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventor: David A. Egolf
  • Patent number: 5694572
    Abstract: In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address.
    Type: Grant
    Filed: February 26, 1992
    Date of Patent: December 2, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventor: Charles P. Ryan
  • Patent number: 5678047
    Abstract: U2G is a software tool that runs on the GCOS-8 operating system and enables it recognize and process the commonly used commands of the UNIX operating system. U2G is a UNIX-GCOS-8 translator that enables the GCOS-8 to recognize, accept and execute UNIX commands. Thus, it enables the UNIX users to work with the GCOS-8 system without prior training. U2G can translate the most commonly used UNIX commands along with their respective options into equivalent GCOS-8 Time Sharing System (TSS) commands. U2G can be used with a "Verbose" mode option which serves to provide descriptive information about the commands and the translation process. U2G has on-line help screens and "explain" pages for all of the important concepts and equivalences. U2G enhances the capabilities of GCOS-8 by supporting the important UNIX concept of "aliasing" and the use of shell variables. Another enhancement to GCOS-8 is support for I/O redirection and simple command procedures.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: October 14, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Forouzan Golshani, Thomas H. Howell
  • Patent number: 5678032
    Abstract: An application such as an interpretative emulator executes a wide range of different classes of emulated program instructions developed for the processor architecture being emulated on a host system which includes an dual integer pipelined execution unit. The sets of RISC instructions which execute emulated program instructions are organized within the emulator so as to be processed as two distinct instruction streams by the dual integer pipelined execution units wherein one of the pipelined unit performs the steps necessary to completing a current or foreground like operation on each emulated program instruction while the other pipelined unit performs the steps of an anticipated lookahead or background like operation on the next emulated program instruction.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: October 14, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: William E. Woods, deceased, Richard A. Lemay, Edward Kumiega
  • Patent number: 5675771
    Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: October 7, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: John L. Curley, Thomas S. Hirsch, James W. Stonier, Kin C. Yu
  • Patent number: 5673418
    Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a network terminal driver (NTD) component operating in the host memory. Configuration command means are provided for initially configuring a host terminal to operate in a plurality of asynchronous driver (ATD) modes implemented by the NTD component. When a terminal has been configured by a user to run applications written for the ATD driver, it sets a mode indication which causes the NTD component to respond to user applications as an ATD driver and determine if each ATD request can be carried out with functionality included within the NTD component.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: September 30, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: James W. Stonier, Michael E. Tessier
  • Patent number: 5671418
    Abstract: U2G is a software tool that runs on the GCOS-8 operating system and enables it recognize and process the commonly used commands of the UNIX operating system. U2G is a UNIX-GCOS-8 translator that enables the GCOS-8 to recognize, accept and execute UNIX commands. Thus, it enables the UNIX users to work with the GCOS-8 system without prior training. U2G can translate the most commonly used UNIX commands along with their respective options into equivalent GCOS-8 Time Sharing System (TSS) commands. U2G can be used with a "verbose" mode option which serves to provide descriptive information about the commands and the translation process. The verbose mode is disabled by a "terse" command.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: September 23, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Forouzan Golshani, Thomas H. Howell
  • Patent number: 5666534
    Abstract: A remote service facility (RSF) unit is integrated into the operating system of the host system being supported. The RSF unit utilizes a standard generic menu interface system (GMIS) unit through which a user can enter different types of commands which results in the display of a number of menu sequences for configuring how the different independently controllable components of the RSF unit will operate in performing remote support functions. The components include a problem detection and reaction component, a system action component and a callback component, each of which operatively couple to the GMIS unit. The components are integrated in a predetermined manner so that collectively, they carry out remote support according to the way in which they were configured.
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: September 9, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Jeremy H. Gilbert, David B. Hout, Michael P. Keohane, David K. Perlow, Daniel G. Peters, Eric J. Storch
  • Patent number: 5663685
    Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop, which phase offset is due to circuit delays in the phase detector. Simultaneous "pump up" and "pump down" signals, present even during apparent phase lock because of such circuit delays, are peak sampled through long lime constant filters and summed to derive a compensating signal which is applied to the reference input to the differential amplifier which controls the local oscillator, thereby exactly counteracting the offset component of the voltage appearing at the signal input to the differential amplifier which is developed during normal operation of the phase detector, filter and summing circuit of the phase locked loop at apparent phase lock.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: September 2, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventor: Donald R. Kesner
  • Patent number: 5664200
    Abstract: A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: September 2, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: George J. Barlow, James W. Keeley
  • Patent number: 5664098
    Abstract: A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service components are extended to accommodate a number of dual decor commands and functions which make host system facilities directly available to ES application programs by concurrent execution of program operations within both the emulator and host system environments. The EMCU includes mechanisms for performing an initial level security validation operation which allows subsequent trusted verification of user identity when dual decor commands or functions are invoked.
    Type: Grant
    Filed: September 23, 1994
    Date of Patent: September 2, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Richard S. Bianchi, Thomas S. Hirsch, Ron B. Perry
  • Patent number: 5659268
    Abstract: Compensation circuits are disclosed for correcting phase offset during apparent phase lock of a dual flip-flop phase detector type of phase locked loop. The phase offset is due to circuit delays in the phase detector which result in the issuance of simultaneous "pump up" and "pump down" signals, present even during apparent phase lock. A second pair of flip-flops (or a single flip-flop) of the same type used in the phase detector is sampled to obtain a compensating signal which is applied to the reference input of a differential amplifier in the loop filter. Each of the second pair of flip-flops is forced to assume a permanent state (for example, set) such that their respective Q and Q-bar outputs are always representative of the logic voltage levels at the corresponding outputs of the flip-flops in the phase detector from which the "pump up" and "pump down" are sourced.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: August 19, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventor: Donald R. Kesner
  • Patent number: 5649090
    Abstract: A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.
    Type: Grant
    Filed: May 31, 1991
    Date of Patent: July 15, 1997
    Assignee: Bull hn Information Systems Inc.
    Inventors: David S. Edwards, William A. Shelly, Jiuyih Chang, Minoru Inoshita, Leonard G. Trubisky
  • Patent number: 5644761
    Abstract: In order to efficiently undertake the micro-steps required to execute an extended instruction in a central processing unit, a main sequence controller and a separate basic operations controller having its own sequencer and the ability to run semi-autonomously are provided. Normally, the main sequence controller determines the operation of the basic operations controller, but, in the case of execution of, for example, a multi-word instruction requiring extended basic operations, the basic operations controller temporarily takes control over the main controller until the extended basic operations have been completed. The result is a relatively simple sequencer that supports tight micro-coded functions where many of the sequence decisions can be predetermined.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: July 1, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Ronald W. Yoder, Ronald E. Lange, William A. Shelly, Russell W. Guenthner, Richard L. Demers
  • Patent number: 5636371
    Abstract: A local host data processing system operating under the control of a local host operating system includes components of a hosted operating system. The host operating system further include a TCP/IP network protocol stack which couples to the communications facilities of the host system connected to a local area network for communicating with a number of remote host systems. Host and hosted operating systems share the same TCP/IP network protocol stack. A virtual network mechanism is configured within the local host system to be operatively coupled to the host network protocol stack and provide access to well-known port application programs. When so configured, the mechanism functions as another LAN to which the hosted operating system is attached. The mechanism transforms the well-known port identifier of each inbound packet into a non-well-known port identifier in addition to other station address identifier fields.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 3, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventor: Kin C. Yu
  • Patent number: 5623667
    Abstract: U2G is a software tool that runs on the GCOS-8 operating system and enables it recognize and process the commonly used commands of the UNIX operating system. U2G is a UNIX-GCOS-8 translator that enables the GCOS-8 to recognize, accept and execute UNIX commands. Thus, it enables the UNIX users to work with the GCOS-8 system without prior training. U2G can translate the most commonly used UNIX commands along with their respective options into equivalent GCOS-8 Time Sharing System (TSS) commands. U2G can be used with a "Verbose" mode option which serves to provide descriptive information about the commands and the translation process. U2G has on-line help screens and "explain" pages for all of the important concepts and equivalences. U2G enhances the capabilities of GCOS-8 by supporting the important UNIX concept of "aliasing" and the use of shell variables.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: April 22, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Forouzan Golshani, Thomas H. Howell
  • Patent number: 5619699
    Abstract: U2G is a software tool that runs on the GCOS-8 operating system and enables it recognize and process the commonly used commands of the UNIX operating system. U2G is a UNIX-GCOS-8 translator that enables the GCOS-8 to recognize, accept and execute UNIX commands. Thus, it enables the UNIX users to work with the GCOS-8 system without prior training. U2G can translate the most commonly used UNIX commands along with their respective options into equivalent GCOS-8 Time Sharing System (TSS) commands. U2G can be used with a "Verbose" mode option which serves to provide descriptive information about the commands and the translation process. U2G has on-line help screens and "explain" pages for all of the important concepts and equivalences. U2G enhances the capabilities of GCOS-8 by supporting the important UNIX concept of "aliasing" and the use of shell variables. Further, the UNIX "piping" feature is made available to GCOS-8.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: April 8, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Forouzan Golshani, Thomas H. Howell
  • Patent number: 5619682
    Abstract: A layered communications bridge mechanism connected between an upper communications layer of a first communications layer mechanism executing in a user level process and a layered communication kernel process of a second system corresponding to the next lower layers of the first communications layer mechanism. The bridge includes an upper bridge mechanism operating to appear to the lowest layer or the layers of the first communications layer mechanism to be the next lower layer of the first layered communications mechanism and a lower bridge mechanism operating to appear to the upper communications layer of the second system kernel process to be the next higher layer of the communications layers of the second system and the upper and lower bridge mechanisms operate to map between the operations of the lower layer of the first communications layer mechanism and the upper layer of the layered communications layers of the second system.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: April 8, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventors: Bruce D. Mayer, Martin Berkowitz, Sudershan K. Sharma
  • Patent number: 5601122
    Abstract: A single device dual action lead forming tool uses standard long nose pliers as the basis of its construction. A set of lead forming elements is incorporated into each plier jaw element. Each set contains forming tooth and forming receptacle elements positioned adjacent to one another in a predetermined manner. The elements of one set are arranged within one jaw element in a reverse order relative to the arrangement of lead forming elements in the other jaw element. When the jaw elements are closed, pairs of like positioned forming tooth and receptacle elements of both sets cooperate together to form both the inner and other leads of a single electronic component in a single operation.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: February 11, 1997
    Assignee: Bull HN Information Systems Inc.
    Inventor: Robert C. Beauchesne
  • Patent number: 5590301
    Abstract: In order to achieve the integration of a plurality of processors, each capable of directly addressing a limited internal space storage range, with a larger external memory space (e.g., a mass memory), the processors are organized into clusters, each having a plurality of processors and a common secondary cache. Each cluster is assigned a two-bit cluster number. Intermediate a primary cache in each processor and the secondary cache in the cluster, an address translator is provided for effecting transformation between internal memory space addresses and external memory space addresses. The external memory space is divided into areas private to each cluster and shared by all the processors. An internal address indicator bit, in conjunction with the cluster number from a requesting processor primary cache, is employed to set up the transformation either to the private external space of that cluster or the shared external space.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: December 31, 1996
    Assignee: Bull HN Information Systems Inc.
    Inventors: Russell W. Guenthner, Leonard Rabins