Abstract: A data processing machine with nonuniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), a given module (10) including a unit (6) to assure data coherence with other modules (20, 40, 60), characterized in that said unit (6) includes at least the following: a first register (81, 101) intended to contain a first physical address of the memory, a second register (82, 102) intended to contain a second physical address of the memory, first means (90, 95, 111, 121, 88, 92, 108) for measuring a quantity of activity relating to the data whose addresses are included between said first physical address and said second physical address, a third register (83, 93, 109) intended to contain a threshold value for measuring said quantity of activity, second means (91, 94, 112, 122) for detecting the exceeding of said threshold value by the quantity of activity measured by the first means.

Abstract: A data processing system (1) comprising distributed data storage resource (D1-D3, FD6, TL4, STOe) under the control of a distributed management unit (DSM1 through DSM6), which may or may not be associated with a server (S1 through S3) . This unit receives, from a centralized management unit (NSM), control programs which dynamically allocate to the unit to a virtual memory space comprising local storage units and all or some of the external storage resources.

Abstract: A device for detecting errors with an integrated self-check, on an integrated circuit comprising a serial link control function for constituting an input-output port (109) between a parallel bus (L2CB, C2LB) and a serial link. The integrated circuit comprises a serializer circuit (109T) on output and a deserializer circuit (109R) on input. An insertion buffer I-sb has each of its outputs connected to one input of an exclusive OR operation with two inputs. The second input of the exclusive OR operation receives a piece of information (o-s) to be transmitted in order to constitute, with the insertion information issuing from the insertion buffer, a piece of substitute information. An additional buffer (I-tb) makes it possible to compare the sequence supplied as output from the exclusive OR with a sequence stored in the additional buffer (I-tb) in order to validate the transmission of the substitute sequence.

Abstract: The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Abstract: A machine with non-uniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), each module comprising a unit (6, 26, 46, 66), the unit (6) comprising at least a first table (8) for managing local accesses to a memory part (5') local to the module (10) and a second table (9) for managing accesses to a memory part (25', 45', 65') remote from the module (10), by means of a system bus (7). The machine comprises:a counter (81) of replacements in the table (8) and a counter (83) of accesses to the first table (8);a counter (91) of replacements in the table (9) and a counter (93) of accesses to the second table (9).The replacement and access counters make it possible to optimize the size of the first and second tables (8) and (9), and/or the strategies for correspondence between virtual addresses and physical addresses.

Abstract: In order to allow a plurality of remote data processing systems (1, 2) to communicate with one another by means of a storage unit (8) shared among these remote systems, each data processing system (1, 2) has the capability to reserve itself temporary exclusive access to the storage unit (8) by means of atomic operations. One particular atomic operation used is comprised of replacing a current value of a register (OPA) in the storage unit (8) with a new value communicated by the data processing system (1, 2) remote from the storage unit, it being understood that the remote data processing system knows an old value of the register (OPA) that is not necessarily equal to its current value. A device is installed in a storage controller (7, 16, 27) for the purpose of executing the atomic operation locally relative to the storage unit (8).

Abstract: A process and system for flushing high-speed buffers in a serial link used between a mover circuit (4) that executes data move operations and at least two memories through at least two channels (400, 401), the data move operations each being constituted by a move request followed by the return of a response or acknowledgement of the request, cyclically with interlacing, the responses following the same pair of serial channels (400, 401) as the requests for which they constitute the acknowledgements. The process comprises:a step for placing the mover circuit (4) into a so-called "absorption" mode of operation,a step for generating a specific write request and a specific read request, each of which comprises a so-called "barrier" marker contained in a control character preceding or following the request,a step for accumulating the responses received, anda step for comparing the responses received.

Abstract: The present invention relates to a process for monitoring a plurality of object types of a plurality of nodes (N1, N2, . . . , Nn) comprising a management node (MN) in an information system. Monitoring is configured and then distributed in a filtered way from the management node (MN) to autonomous agents (SAA), an autonomous agent being installed in each node to be monitored in order, by providing intertype correlation, either to locally process the different object types or all of the objects of a domain called a global object, defined generically, or to feed back information to be displayed to the graphical interface of the management node, each agent comprising a plurality of specific modules (SM1, SM2, . . .

Abstract: The present invention relates to a system and process for managing and processing object transactions in a network of distributed resources operating in the client-server mode, wherein the client sends a request to at least one transaction object contained in at least one of the servers (RS1, RS2, etc.) distributed across the network, while a transaction manager dialogues with a resource manager (RM) through a predefined interface by means of a transaction validation protocol. This system is noteworthy in that it achieves the implicit integration of resource managers (RM) adapted to the predefined interface, so as to integrate the participation of existing or future resource managers (RM) into a distributed transaction managed by the transaction manager, by providing objects capable of participating in the transaction validation protocol implemented by the transaction manager, which objects address the resource managers through the predefined interface.

Abstract: The invention relates to data processing machine network architecture and more particularly relates to the load balancing of data servers. A data server (3) is constituted by at least two server data processing machines (1, 2) capable of providing the same services. The server data processing machines (1, 2) have the same physical address MAC0 to which the same network protocol address is assigned in order to establish connections of client machines to the server (3), which is considered as a single virtual machine. Each server data processing machine comprises filtering means so that each connection of a client machine (5, 6, 7, 8, 9, 10) to the virtual machine corresponds to a unique connection effective with one and only one server data processing machine (1 or 2). The filtering means of each server data processing machine (1, 2) take into account at least one indicator of the status of each server data processing machine (1, 2) having the same physical address MAC0.

Abstract: The invention relates to a method of correction of corrupted data stored in a memory location by scrubbing. The memory is associated with an error correcting code device which corrects the data transmitted to a user requesting them. The method comprises three steps. During a first step, the data is read from the memory at an address contained in a first register, corrected, and stored into a second register. A reservation is created. During a second step, if a reservation exists the data contained in the second register is written back into the same memory location. The reservation is cleared and a particular field of a condition register is modified. If a reservation does not exist, the second step is completed without altering the memory location. During the third step, the status of the condition register is checked. If the test is positive the process is ended, the scrubbing being successful; if not, an iteration of the three above steps is executed.

Abstract: In order to move data blocks from a source memory unit (8, 9, 12) to a target memory unit (12, 8, 9) by means of a data path (5, 6, 7), wherein the blocks moved are not necessarily framed in the blocks of the source memory and the target memory, an electrical circuit makes it possible to perform a framing with a granularity equal to the width of the data path. To reduce latency, the framing is done by a shift register with a storage capacity reduced to that of a single block.

Abstract: The invention relates to a process for synchronizing a computer system with regard to a date which changes over time. The computer system comprises one or more modules (1, 2, 3, 4), each module (1, 2) comprising several processors (10, 11, 12, 13, 20, 21, 22, 23) regulated by a clock specific to a module (1, 2). Each processor (10, 11, 12, 13, 20, 21, 22, 23) comprises a private register TBR (16, 17, 18, 19, 26, 27, 28, 29) adapted to contain a value corresponding to said date and to undergo an incrementation by the clock specific to the module (1, 2) comprising this processor (10, 11, 12, 13, 20, 21, 22, 23).

Abstract: The present invention relates to an application integration tool for integrating applications into a data processing platform which includes structure for hosting applications, making it possible for applications editors and customers having at least one application to integrate, to configure the services of the platform so that the application will be supported by the platform as soon as it is installed. The integration tool allows any application to be integrated to benefit automatically from the services offered by the platform as soon as it is installed, and facilitates the launching of applications at a plurality of sites.

Abstract: The display screen (11) is made of pixels (P) connected to one edge (11a) of the screen by wires (12) separated by a given pitch (s) so as to be controlled by respective terminals (18) of integrated circuits (16) outside the screen. The terminals (18) of each integrated circuit are disposed in a plurality of parallel rows (19) in which they are separated from one another by a pitch (Sm) equal to several times the pitch of the wires. Each integrated circuit is mounted on a connecting support (10) formed by an insulating film (21) carrying conductive tracks (23) connecting the terminals of the integrated circuit to the corresponding wires of the screen, the tracks extending substantially at the pitch of the wires. The mounting is done simply by collective reflow of bumps between the tracks (23) and the terminals (18), and the support (10) makes it possible to test the integrated circuits before they are mounted on the screen.

Abstract: A process for the management of multiple inheritance for application in a system or language employing persistent and shared objects. According to this process, the format of an object is maintained unchanged when it is being loaded from persistent space into virtual space. Moreover, each class producing an object is associated with an identifier of the class constant in all those applications utilizing the class as well as through all the recompilations. The structure of the object is thus independent of the address of storage in memory and of the code of the class producing this object. Finally, according to the present process, an addressing path permitting the management of inheritance is imposed via different tables.

Abstract: Electrical circuit (5) arranged to move data blocks from a source memory unit (8, 9, 12) to a target memory unit (9, 12, 8) by a data path (5, 6, 7), to send, in a given order, requests to read blocks in the source memory, to generate an end marker in the request to read the last block of the source memory, to receive the blocks read, in the form of response messages, in the order in which the requests were sent, and to send requests to write the received blocks, in the target memory, during receiving of response messages until receiving a message from the source memory with the end marker.

Abstract: The present invention relates to a process and system for real-time monitoring of a data processing system for administration and maintenance support of the data processing system in the operating phase, which data processing system communicates in a client/server mode through interconnected networks (W), each client (WCL) comprising a browser (BRO) which supports a high-level hypertext language. Intelligent agents are installed in each server (WSE) for running, after the phrasing of client requests, a check on the status of each server, measuring and storing parameter information indicating the status and the behavior of the server at a given moment, which parameter information is automatically collected as a function of domains examined and systematically processed by the server so as to be offered in the form of presentation reports contained in dynamically evolving pages while the client's browser accesses the dynamic pages having the collected and processed information responding to a request.

Abstract: For the obtainment of a unique number identifier called a ticket indentifying a task or an event in a multi-node data processing system (SYS), a master node (Ny) for distributing the ticket in the system is designated, and it includes a ticket generator (TICKy:VALy, SESSy, COUNTy) whose address (TICK.sub.-- ID) is stored in a reference register (REF) of each node. When a node (Nx) requests a ticket, it reads the address (TICK.sub.-- ID) in this register and thus accesses the ticket generator of the master node (Ny). A backup or substitute node (Ns) can replace the master node (Ny) in case of a failure (TICK-MISS).

Abstract: In a multinode information system (SYS), a processor (Pxm) of a first node (Nx) emits a message of predetermined size (MESS) in the form of a write operation in the communication module (ISLx) of the first node and transmits it to the communication module (ISLy) of a second node (Ny), where it is stored in a queue of messages received (FIFO-MGT), in the order of their reception, then dequeued by a processor (Pyn) of the second node (Ny) in the form of a read operation in the communication module (ISLy) of this node so that the information contained in the message can be processed.