Abstract: A low voltage sixteen bit digital-to-analog converter operable between +5 and -5 volt power supplies and capable of providing output voltage levels to within about 1.4 volts of +V.sub.CC and -V.sub.CC includes a circuit for external adjustment of the bit current of a particular bit of the digital-to-analog converter, which circuit produces a constant adjustment current that is summed with that bit current over a wide range of processing parameters and temperature, and requires only a single terminal for connection of an external potentiometer by means of which the bit current is adjusted and a small value filter capacitor for filtering out noise generated by an internal zener diode voltage reference circuit.

Abstract: A differential common base amplifier circuit includes first and second source follower field effect transistors that apply a differential input signal between the emitters of first and second bipolar transistors having a common base connection. An output circuit connected to the collector of the first bipolar transistor includes a bipolar emitter follower transistor having its emitter connected to a first field effect transistor which is connected to the emitter of the emitter follower transistor. The gate of the first field effect transistor is connected to the gate of one of the source follower field effect transistors. Process-caused variations in the gate to source voltage characteristic of the second source follower field effect transistor and the first field effect transistor are applied equally to the emitter and collector of the second bipolar transistor. This avoids input offset errors due to base width variations in the second bipolar transistor.

Abstract: An amplifier having a very high gain-bandwidth product includes a first operational amplifier having its positive input connected to the amplifier's input. The output of the first operational amplifier is connected to the base of a transistor, the emitter of which is coupled by a gain-setting resistor to ground and is also directly connected to the negative input of the first operational amplifier. The collector of the transistor is connected by a resistive load to a supply voltage and is also directly connected to the negative input of a second operational amplifier. The output of the second operational amplifier is coupled by a capacitor back to its negative input. The output of the second operational amplifier is coupled by a feedback resistor back to the emitter of the transistor. The output of the second operational amplifier is connected to the output terminal of the amplifier.

Abstract: An analog-to-digital converter is used in conjunction with a digital to analog converter and a comparison network to provide a group of digital signals that, when applied to a digital-to-analog converter, produce an output signal approximating an applied input signal. The analog-to-digital converter includes a clock circuit, a series of bistable multivibrator circuits, a master latch circuit, a plurality of slave latch circuits, and associated logic circuits. The bistable multivibrators are arranged to produce a sequence of activation signals in response to operation of the clock circuit. The activation signals serve to place slave latches circuits sequentially in a positive logic status temporarily, each slave latch output terminal being associated with a binary signal of decreasing significance in approximating the applied input signal. The output signal of the digital-to-analog converter is compared with the applied input signal.

Abstract: A plurality of input stages having their outputs connected to provide differential currents to a load. When a bias current flows through a selected one of the input stages, the differential currents are provided in response to a differential signal provided to the selected stage. The input stages are each comprised of a pair of emitter-coupled transistors. Resistors are connected in series with the emitters of the transistors and the bias current is directly proportional to absolute temperature. The resistors may be adjusted to cause the offset voltages of the input stages to substantially equal zero at all temperatures.

Abstract: An article for dissipating heat generated by an alphanumeric display which is mounted on an electronic circuit board. The article includes a heat sink which is coupled to the underside of the alphanumeric display. The heat sink has at least one transfer member which extends through the electronic circuit board and is coupled to a dissipation plate. The dissipation plate is exposed to an environment which is removed from the immediate environment of the electronic circuit board. Heat generated by the alphanumeric display is transferred to the heat sink and through the transfer member(s) to the dissipation plate. The heat is then dissipated in an environment which is removed from that of any electronic components mounted on the electronic circuit board.

Abstract: A process and apparatus for sealing electronic packages and lids involves placing a heater preform device between the sealing surfaces of the package and lid. If the package and lid are ceramic, the preform may be metallic having a glass coating fused thereto. Similar glass coatings would be fused to the sealing surfaces of the package and lid. The metallic portion of the preform is then heated by, for example, passing an electrical current therethrough to melt the glass and effect the seal.

Abstract: In a digital to analog converter, a circuit for improving the performance of digital to analog converters by reducing and minimizing the variation in analog ground current is disclosed. The resulting digital to analog converter has reduced variation in output signal, the digital to analog converter can provide a more accurate representation of the input digital signal.

Abstract: A process and apparatus for sealing electronic packages and lids involves placing a heater preform device between the sealing surfaces of the package and lid. If the package and lid are ceramic, the preform may be metallic having a glass coating fused thereto. Similar glass coatings would be fused to the sealing surfaces of the package and lid. The metallic portion of the preform is then heated by, for example, passing an electrical current therethrough to melt the glass and effect the seal.

Abstract: In a circuit in which a common-source junction field effect transistor (JFET) is cascoded with a JFET element, current diversion or division circuits are used to divert a majority of the current passing through the input amplifier stage so that it bypasses the cascode FET without compromising the primary circuit function. The bypassing function is achieved by a current mirror, a current mirror-like circuit, or similar devices such as current sources, current splitters and the like and the circuits may be ratioed to more precisely control the bypass current by the use of emitter area scaling, ratioed emitter degeneration resistors, or both. The resultant cascode circuit is relatively noise-free and can easily be implemented into a monolithic integrated circuit without using excess or unrealistic die areas.

Abstract: A trimmable resistive scaling network suitable for use in digital-to-analog converters or the like. At least two trimmable resistors with low order integral relative values provide for either scaling up or scaling down with high accuracy.

Abstract: A latch circuit utilizes a series-gated, emitter coupled logic structure including a current source providing a gate current substantially proportional to temperature for developing an output signal swing substantially proportional to temperature, thereby allowing the output signal swing to have a reduced magnitude at nominal temperatures. The load across which the output signal is developed includes a resistor coupled in series with a semiconductor P-N junction. Emitter areas of emitter-coupled transistor pairs within the latch circuit are mismatched for creating an offset tending to compensate changes in the voltage across the semiconductor junction within the load resulting from the switching action of the latch circuit. A bias circuit maintains the switching threshold reference voltage substantially intermediate the output signal swing.

Abstract: A bar code reading system having a wand that detects variations in light reflected by bars and spaces of the label produces a sequence of corresponding pulses and intervals as the wand scans the label. The entire sequence of pulses and intervals is input to a microprocessor system which produces corresponding digital duration numbers. The microprocessor system computes a reference number for a first character of the label and compares each digital duration number of the character to the reference number to compute a binary number with bits that are a "one" or a "zero" according to whether corresponding digital internal numbers exceed or are less than the reference number. If the number of "ones" in the binary number is too low or too high, the microprocessor decreases or increases the reference time, compares the digital duration number with the adjusted reference number, and re-determines if the resulting value of the binary number has the correct number of "ones".

Abstract: A band-gap voltage reference circuit which incorporates a band-gap differential amplifier supplied with constant, temperature-independent current, a high gain differential-to-single-ended converter, temperature-compensated negative feedback means and a common source of biasing to serve as a device to provide an output reference voltage so that the output reference voltage is precise and independent of variations in temperature, loading and power supply voltage. An improved amplifier is also disclosed.

Abstract: A band gap voltage reference circuit includes first and second NPN transistors coupled as differential pair having ratioed emitters, to produce an offset voltage, and third and fourth emitter-coupled PNP transistors connected as a current mirror to function as load devices for the first and second transistors. The emitters of the third and fourth transistors are coupled to a current source and also to a fifth PNP emitter follower transistor which drives the base of a sixth emitter follower transistor connected to the collector of a seventh transistor, the emitter of which is connected to a series string including first and second resistors. The emitter of the seventh transistor is coupled to the base of the first transistor and the junction between the first and second resistors is coupled to the base of the second transistor. The emitter of the sixth transistor is coupled to series connected third and fourth resistors, the junction of which is coupled to the base of the seventh transistor.

Abstract: An integrated circuit digital to analog converter includes circuitry having first and second resistors in a R/2R resistor ladder which scales bit current contributions to an analog output current. Each of the first and second resistors have a respective terminal connected to the collector of a bit current transistor, the emitter of which is connected to the emitter of a waste current transistor. The digital to analog converter includes a metal ground voltage conductor having a "shared node" and a distributed resistance between one side of the shared node and a main ground voltage connection. The collector of the waste current transistor and a second terminal of the first resistor are both connected directly to the shared node. In operation, the waste current transistor switches waste current into the shared node, rather than into a separate waste current ground conductor.

Abstract: A process and apparatus for sealing electronic packages and lids involves placing a heater preform device between the sealing surfaces of the package and lid. If the package and lid are ceramic, the preform may be metallic having a glass coating fused thereto. Similar glass coatings would be fused to the sealing surfaces of the package and lid. The metallic portion of the preform is then heated by, for example, passing an electrical current therethrough to melt the glass and effect the seal.

Abstract: A ladder network includes a plurality of cascaded prototype network sections connection in cascade and terminated with a termination resistor. The sections each provide gains of 1/2, 2/5, 1/5 and 1/10. Linear circuits are also disclosed which utilize at least one amplifier and the ladder network in a feedback loop.