Abstract: A planar transformer includes a multilayer printed circuit board having a plurality of spiral windings formed by metalization on various surfaces of the printed circuit board. A ferrite core assembly includes first and second core sections disposed on opposite sides of the printed circuit board and completely confining the conductors of the spiral windings. Each core section includes a thin, flat plate. The two flat plates are integral with or abut thin post sections that are thick enough to allow the printed circuit board to be accommodated between the first and second core sections. In one embodiment of the invention, the planar transformer is incorporated on the printed circuit board with other circuitry to form a low noise battery charger which is encapsulated in a male power connector.

Abstract: A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.

Abstract: A low noise battery charger includes a rectifier to convert AC line voltage to a rectified sinusoidal voltage that is applied to a primary winding of a transformer. Another rectifier coupled to a first secondary winding applies a charging current to a battery. A switch coupled in series with the primary winding controls current therein. A rectifier coupled to another secondary winding produces a battery condition voltage. An incrementing signal synchronized with the rectified sinusoidal voltage increments a ratchet DAC until its output voltage exceeds the battery condition voltage. A low charging mode signal is produced when the battery condition voltage falls a certain amount below the DAC output voltage.

Abstract: A reference voltage circuit in an integrated circuit analog-to-digital converter includes a band gap circuit, a first field effect transistor coupling an output conductor of the band gap circuit to a first external bypass capacitor and a non-inverting input of a buffer circuit. A second field effect transistor couples the first conductor to a non-inverting input of the buffer circuit. An output of the buffer circuit is coupled to an inverting input thereof. The first and second field effect transistors are turned on during conversions, during which the first field effect transistor and the first bypass capacitor coacting to filter high frequency noise produced by the band gap circuit to apply a precise reference voltage to the non-inverting input of the buffer circuit.

Abstract: A modified sign-magnitude DAC includes first internal DAC circuitry including a first number of bit switch circuits responsive to an input word including a sign bit and a digital data word. Each bit switch circuit is coupled to a corresponding current source transistor. Second internal DAC circuitry includes the same number of bit switch circuits responsive to the input word. Each bit switch circuit of the second internal DAC circuitry is coupled to a corresponding current source transistor. The same number of binarily weighted bit current determining resistor circuits corresponding to bits of the digital data word are connected to a reference voltage conductor. The emitter of the current source transistor of each bit switch circuit of the first internal DAC circuitry is coupled by a first gain balancing resistor to the corresponding bit current determining resistor.

Abstract: A circuit for preventing analog-to-digital conversion errors due to MOS threshold shifts produced in a comparator during successive approximation testing of MSB and LSB groups of binarily weighted bit capacitors includes a first amplifier that amplifies voltage changes produced on a charge distribution conductor connected to the bit capacitors during successive approximation testing of the bit capacitors of the MSB group. The output of the first amplifier subjects a MOSFET in an input stage of the comparator to sufficiently large gate-to-source voltages to produce an MOS threshold shift in the MOSFET. During successive approximation testing of bit capacitors of the LSB group, a second amplifier amplifies signals representative of voltage changes produced on the charge distribution conductor and applies the amplified signals to the same MOSFET.

Abstract: A unity gain amplifier of the diamond follower type provides the combination of negligible input offset voltage, high slew rate, and high bandwidth by providing first and second opposite polarity current mirror circuits which respond to currents flowing through first and second input transistors to boost current available to charge parasitic capacitances during fast rise times and fast fall times of an input pulse. The rapid charging and discharging of the parasitic capacitances eliminates degradation in the rise and fall times of an output pulse produced by the unity gain amplifier. The gains of the first and second current mirror circuits have values that result in critically damped high frequency response of the unity gain amplifier in response to high speed transistions of the input signal. Darlington output stages are used to avoid frequency response peaking due to current gain rolloff of the output transistors at high currents and high frequencies.

Abstract: In an analog-to-digital converter, a circuit for sampling an analog input signal that has a signal range above and below a ground reference voltage includes a divider circuit scaling the analog input signal down to a lower magnitude such that all values of the scaled analog input signal are above the ground reference voltage. The scaled down analog input signal is applied to a source electrode of a sampling MOSFET. A body-to-source voltage of the sampling MOSFET is maintained at approximately zero volts by applying the scaled down signal to a non-inverting input of a first operational amplifier and applying an output voltage produced by the first operational amplifier to its inverting input and a body electrode of the sampling MOSFET. A gate-to-source voltage of the sampling MOSFET is maintained at approximately 1.

Abstract: A circuit for generating a plurality of timing signals includes a plurality of cascade-connected delay cells, each having an input coupled to an output of another, and a plurality of latches. Set inputs of various latches are coupled to outputs of various delay cells to determine times of occurrence of leading edges of various timing pulses. Reset inputs of the various latches are coupled to outputs of various delay cells to determine times of occurrence of trailing edges of various timing pulses. The circuit includes a phase detector having a first input coupled to receive a clock signal and a second input coupled to an output of one of the delay cells to receive a signal indicative of propagation of a logic state through a first group of the delay cells, to produce an adjustment signal indicative of whether the phase of the indicator signal is ahead of or behind the phase of the clock signal.

Abstract: A track-and-hold circuit that consists of an operational amplifer wherein the same capacitors are used for phase compensation and as differential holding capacitors. The circuit is switched from track to hold by turning off the input stage by reverse biasing base-emitter junctions through current steering in combination with resistor clamping. Low impedance during the hold mode is maintained because one half of the differential compensation path is connected to the output. Feed-through is eliminated by cascoding the first stage and turning off the cascode devices through current steering with resistor clamping during the holding mode. The holding capacitors' droop due to bias currents is minimized by current cancellation of the second stage.

Abstract: A low noise battery charger includes a rectifier to convert AC line voltage to a rectified sinusoidal voltage that is applied to a primary winding of a transformer. Another rectifier coupled to a first secondary winding applies a charging current to a battery. A switch coupled in series with the primary winding controls current therein. A rectifier coupled to another secondary winding produces a battery condition voltage. An incrementing signal synchronized with the rectified sinusoidal voltage increments a ratchet DAC until its output voltage exceeds the battery condition voltage. A low charging mode signal is produced when the battery condition voltage falls a certain amount below the DAC output voltage. Flow of current through the primary winding is controlled by operating the switch at a relatively high frequency and by producing constant turn off times for the switch and also by modulating turn on times for the switch in response to the signal indicative of primary winding current.

Abstract: A current-integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to a ground voltage and an inverting input coupled to an input conductor carrying an analog input current. An integrating capacitor having one terminal coupled to the input conductor and another terminal coupled to an output of a digital-to-analog converter. A tracking circuit is coupled to an output of the comparator to apply digital signals to inputs of the digital-to-analog converter to maintain the inverting input close to a virtual ground voltage. A digital filter filters the digital signals to produce a digital output signal that precisely represents the input current.

Abstract: An interpolation DAC includes first and second registers connected to receive the X least significant and Y most significant bits of a digital input word, and are clocked to latch the X least significant bits and Y most significant bits at a first clock rate. An adder has a first group of X inputs, a second group of X inputs, X outputs, and a carry output. A third register has X inputs, and X outputs coupled to the second group of X inputs of the adder. The third register is clocked to latch the outputs of the adder at a second clock rate which is the oversampling ratio times faster than the first clock rate. A Y bit plus 1 bit DAC in which the 1 bit is a duplicate of the least significant of the Y bit section has its most significant Y bits coupled to receive the outputs of the second register. The duplicate LSB is connected to receive the carry output from the adder. A low pass filter responsive to the Y bit plus 1 bit DAC produces an analog output representative of a value of the digital input word.

Abstract: A method of making a hybrid integrated circuit includes bonding an insulative film to a first area of a lead frame flag, a second area of the lead frame flag being exposed. A plurality of individual metalized strips and a first flag area are formed on the film. A first integrated circuit chip such as a low power MOS chip, is bonded to the first flag area, and a second integrated circuit chip, such as a high power bipolar chip, is bonded to the second area of the lead frame flag. Bonding wires are bonded to connect various bonding pads and fingers of the lead frame of the two integrated circuit chips to various metallized strips on the insulative film. The chips, bonding wires, lead frame flag, lead frame fingers, and insulative film are encapsulated in plastic by transfer molding.

Abstract: A high speed, high current analog switching circuit includes a switch JFET having its drain electrode connected to an analog input voltage terminal and a source electrode connected to an analog output voltage terminal. The gate electrode of the JFET switch is connected to switching control circuitry. The analog switching circuit includes circuitry that prevents the source-gate PN junction of the switch JFET from ever being forward biased more than approximately 0.2 volts. This prevents the charge storage capacitance of that PN junction from ever increasing to such high values (e.g. 100 to 1000 picofarads) that discharging of the charge storage capacitance through the channel resistance of the switch JFET takes excessively long periods of time. Rapid equalization of the analog output voltage and analog input voltage to within approximately 10 microvolts of each other is thereby achieved.

Abstract: A low distortion capacitor sampling circuit includes a sampling MOSFET, the source electrode of which receives a time-varying input voltage to be sampled. A bootstrap capacitor has a first terminal connected to the gate electrode of the sampling MOSFET and to a first MOSFET that charges the first terminal of the bootstrap capacitor to a first voltage in response to a first control signal. A delayed second control signal is applied to the gate of a second MOSFET the drain electrode of which is connected to a second terminal of the bootstrap capacitor to keep the pulldown MOSFET on until the charging of the sampling capacitor is complete. Then a third control signal turns on a third MOSFET, boosting both terminals of the bootstrap capacitor. The second control signal then turns the third MOSFET off, electrically isolating the gate electrode of the sampling MOSFET. Changes in the time-varying input voltage are coupled by the gate-to-source capacitance of the sampling MOSFET to the gate electrode thereof.

Abstract: A subranging analog-to-digital converter (ADC) that comprises a biasing architecture including a single string of transistor current sources used to generate the reference digital-to-analog converter (DAC) bit currents, the low-resolution flash ADC reference ladder voltage, and the ADC bipolar offset voltage. The reference DAC resistors, low resolution voltage reference ladder resistors, error amplifier gain set resistors, and the bipolar offset resistors are all constructed from the same material and using the same physical construction, so that they match with high precision and track over process and temperature. In one embodiment, the low-resolution flash ADC is itself implemented as a two-step parallel subranging ADC, comprising a most-significant-bit reference ladder and a least-significant-bit reference ladder, and includes an internal flash DAC whose bit currents are also provided by the same single string of transistor current sources.

Abstract: A low distortion differential amplifier circuit includes a primary differential circuit stage and a secondary differential circuit stage. The primary differential circuit stage includes first and second transistors each having a first current source coupled to the emitters of the first and second transistors. A first load device is coupled to the collector of the second transistor. The secondary differential circuit stage includes third and fourth transistors. A second current source is coupled to the emitters of the third and fourth transistors. The bases of the third and fourth transistors are coupled to the collectors of the first and second transistors, respectively. A second load device is coupled to the collector of the fourth transistor. A fifth transistor has its emitter and collector coupled to a supply voltage conductor and the base of the third transistor, respectively.

Abstract: A method and apparatus for converting a plurality of digital signals to an analog signal and m-bit digital-to-analog converter having an LSB current switch. A most significant m bits of an .[.m.]. .Iadd.n .Iaddend.bit digital signal are applied to m bits, respectively, of the m bit digital-to-analog converter, and successive values of the n bit digital signal are substituted at a first frequency. An interpolation signal is produced at the first frequency. A least significant n-m bits of the n bit digital signal are applied to the interpolation circuit to cause it to interpolate between successive values of the n bit digital signal. An LSB current switch distinct from the m bit digital-to-analog converter produces an output signal in response to the interpolation signal. An analog output signal produced by the m bit digital-to-analog converter is combined with the output signal produced by the LSB current switch to produce an analog output signal with n bit resolution.