Abstract: A low cost, high frequency isolation amplifier includes a first voltage-to-frequency converter producing a first pair of complementary pulses in response to an analog input signal and applying them to a pair of low capacitance capacitors constituting the isolation barrier. The isolation barrier differentiates edges of the first pair of pulse signals and applies the resulting signals to inputs of a sense amplifier including a differential amplifier, a pair of comparators, and a flip-flop to precisely reconstruct the first pair of complementary pulse signals, which then are fed into a decoder circuit including a phase locked loop. The phase locked loop includes a phase detector receiving the reconstructed pair of complementary pulse signals and a second pair of complementary pulse signals produced by a second voltage-to-frequency converter.

Abstract: A programmable gain instrumentation amplifier includes first and second differential subcircuits, each of which includes first and second input transistors, a first constant current source, first and second gain selection transistors, an output transistor, and a second constant current source. The bases of the first and second input transistors of the first and second subcircuits are connected, respectively, to first and second input terminals. The emitters of the first and second input transistors are connected to first and second gain resistors, respectively, and also are connected to collectors of the first and second gain selection transistors, respectively. The bases of the first and second gain selection transistors of the first and second subcircuits are coupled to first and second gain selection signals, respectively. Collectors of the first and second input transistors are connected to the first constant current source.

Abstract: This disclosure is a integrated circuit reference diode having improved manufacturability and electrical characteristics. The improved diode results from a structure and process which both reduces the subsurface breakdown and enhances the surface breakdown.

Abstract: A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The sampling waveform digitizer system comprises a sampling comparator for comparing a sampled input signal with a first signal. An integrator coupled to the comparator provides an output signal from the integrator and becomes the first signal. An analog to digital converter provides the digital representation of the analog waveform. A controllable delay is provided for selecting a period of time for sampling the input signal by the comparator. A control device is provided for controlling the time the comparator samples the input signal. These combination of system features allow the digitizer to receive high speed analog waveforms and convert them to an accurate digital representation of the previously described high speed analog waveform.

Abstract: A CMOS digital-to-analog converter includes a modified R-2R resistive ladder network connected to 16 pairs of bit switches responsive to the various digital inputs to produce an internal analog voltage representative of the digital input. Each pair of bit switches includes an N-channel MOSFET and a P-channel MOSFET. The on resistance of the P-channel MOSFET is adjusted to precisely match that of the N-channel MOSFET by driving the gate of each P-channel MOSFET with the output of a CMOS inverter referenced between V.sub.CC and a reference voltage that is adjusted to cause the on resistances of a P-channel "monitor" MOSFET and an N-channel "monitor" MOSFET to be equal. A reference voltage is generated by a circuit that generates a temperature-invariant source current from a V.sub.BE difference between first and second transistors, causes part of it to flow through first, second, and third resistors, the third resistor having a voltage across it established by the V.sub.

Abstract: A vacuum chuck for securely holding integrated circuit hybrid package substrates in fixed relationship to an X/Y table that is subjected to severe repeated lateral acceleration and decceleration forces to prevent appreciable lateral displacement of the package substrate relative to the X/Y table. A plurality of shallow, closed loop grooves are disposed in the chuck. A resilient O ring is disposed in each groove and normally extends a small but precise amount above the surface of the base. A vacuum path opens into each region circumscribed by an O ring. When a package substrate is positioned on an O ring and the vacuum then is applied, the O ring is compressed, causing the sides of the O ring to tightly engage the walls of the groove, preventing the O ring from "rolling" in the groove as a result of lateral acceleration and decceleration forces on the package.

Abstract: Large "inactive" N+ regions are provided in P channel junction field effect transistors (JFETs) or NPN transistors immediately adjacent to "active" areas thereof to getter impurities away from the active areas. The ratio of inactive N+ area to the total area of the transistors is selected to provide suitably low noise measurements at low frequencies. Low noise amplifier circuitry is provided wherein all transistors in the AC signal path include unusually large ratios of inactive N+ area to total transistor area in order to provide greatly reduced low frequency noise levels.

Abstract: A two-terminal temperature-compensated current source includes a first transistor having its emitter connected to a first terminal, its base connected to the base of a second transistor, and its collector coupled to a current mirror. The second transistor has its emitter coupled to the first terminal by a first resistor and its collector coupled to the current mirror. A second resistor is coupled between the first terminal and the base of the first transistor. The current mirror is coupled between a second terminal and the collectors of the first and second transistors so that all current supplied to the current mirror from the second terminal flows into the collectors of the first and second transistors. A third transistor has its base coupled to the collector of the first transistor, its emitter coupled to the base of the first transistor, and its collector coupled to the second terminal.

Abstract: A dual cavity semiconductor package containing a high voltage (greater than 1500 volts) isolation amplifier includes a ceramic substrate with tungsten metalization thereon defining die bonding and wire bonding sites and interconnections in the two cavities for input and output circuitry of the isolation amplifier, respectively. The metalization also defines a pair of precisely matched planar fringe capacitors forming a high voltage small signal isolation barrier located between the two cavities. A layer of ceramic having apertures therein defining the two cavities is laminated over the substrate. The assembly is cofired at about 2,000.degree. Centrigrade, causing ceramic to fill the gaps between the conductors of the fringe capacitors, providing very high voltage isolation therebetween. Separate tungsten sealing rings are provided around the peripheries of the cavities on the top surface of the second layer.

Abstract: A square toroid transformer is assembled on a ceramic hybrid integrated circuit substrate. The primary and secondary windings of the transformer are provided on opposite arms of a square toroid ferrite core by providing first and second groups of spaced, parallel metal conductors on the surface of the ceramic substrate and adherent thereto, and an insulative layer over the first and second groups of conductors, leaving their respective end portions exposed. The square toroid ferrite core, coated with dielectric material, is attached to the insulative layer. Wire bonds in planes perpendicular to the longitudinal axes of the opposite arms each are wire bonded, respectively, to an inner end of one of the metal conductors and an outer end of an adjacent one.

Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.

Abstract: An apparatus for selective backlighting individual transluscent keys of a terminal keyboard includes a horizontal, double-sided printed circuit board having a number of right angle LEDs equal to the number of backlit keys mounted on its bottom surface. A plurality of clearance holes in the printed circuit board admit a plurality of vertical light pipes that are integral with a transparent substrate. Integral alignment bosses on a bottom surface of the substrate fit precisely in corresponding holes of the printed circuit board. Each light pipe has a rectangular cross section and a 45 degree inclined bottom surface. A horizontal light beam emitted by a LED passes through a vertical wall of a light pipe, strikes its inclined bottom surface, and is reflected up through the light pipe into a recess within a key. The substrate supports a rubber sheet in which the keys are molded and a switch contact layer with printed conductors thereon.

Abstract: A pressure sensing device including a single crystal of silicon configured to have a diaphram portion, a frame portion and associated circuitry formed on the crystal is described. Piezo-resistive elements on the boundary of the frame and the diaphram portions of the crystal respond to changes in pressure. The piezo-resistive elements, associated elements, and connecting conducting paths are formed by thin film and/or doping techniques to provide a monolithically integrated circuit. The elements are passive and require only application of input voltages and detection of output signals to provide an operative component. Trimmable resistors are provided for compensation and resistive adjustment, and at least one resistive element provides temperature compensation.

Abstract: Circuitry and method for compensating for the junction leakage current of a reverse-biased semiconductor device. Compensation is effected by trimming the leakage of a compensating device at a high temperature in order to accurately compensate the leakage current over a broad range of temperatures. Potential applications include reduction of the input bias current of an amplifier or differential amplifier.

Abstract: A 12 bit, 10 megahertz subranging analog-to-digital converter produces a sampled analog input signal. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sample analog signal to produce a residue signal by means of a high speed amplifier having first and second multiplexed differential input stages, the first input stage having differential inputs receiving the sampled analog input signal and the analog signal produced by the 7 bit DAC. The second differential input stage has one input connected to ground and the other input resistively coupled to the output of the high speed amplifier. The output of the high speed amplifier is resistively coupled to the second input of the first and second differential stages. The multiplexed input high speed amplifier produces an intermediate input level until the output of the DAC is stable.

Abstract: A low cost, high frequency isolation amplifier includes a first voltage-to-frequency converter producing a first pair of complementary pulses in response to an analog input signal and applying them to a pair of low capacitance capacitors constituting the isolation barrier. The isolation barrier differentiates edges of the first pair of pulse signals and applies the resulting signals to inputs of a sense amplifier including a differential amplifier, a pair of comparators, and a flip-flop to precisely reconstruct the first pair of complementary pulse signals, which then are fed into a decoder circuit including a phase locked loop. The phase locked loop includes a phase detector receiving the reconstructed pair of complementary pulse signals and a second pair of complementary pulse signals produced by a second voltage-to-frequency converter.

Abstract: In a data processing system in which the program memory unit and the internal data memory unit are separately addressed, and which special instructions for transferring data between these two units are available, apparatus and method are described for increasing the memory available for the internal data memory unit. The increased storage space takes the form of an auxiliary data memory unit that is activated when the special instruction for the transfer of data signal groups between the program memory unit and the data memory unit are evoked. Apparatus is provided for identifying the presence of the special instructions, and this identification generates the signals for inactivating the program memory unit and for activating the auxiliary data unit for the purposes of transfer of data signal groups between the internal data unit and the auxiliary data memory unit.

Abstract: A subsurface zener diode is formed in an N.sup.- epitaxial region formed on a P type substrate. The N.sup.- epitaxial region is isolated by a P.sup.+ isolation region. An N.sup.+ buried layer region is disposed between a portion of the N.sup.- epitaxial region and the P type substrate. A first P.sup.+ region is formed in the middle of the N.sup.- epitaxial region at the same time as the P.sup.+ isolation regions. Second and third adjacent P.sup.+ regions also are formed in the N.sup.- epitaxial region adjacent to and slightly overlapping the first P.sup.+ region, all three P.sup.+ regions terminating at the N.sup.+ buried layer. An N.sup.+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P.sup.+ regions. Two other opposed edges of the N.sup.+ region extend beyond the other edges of the first P.sup.+ region, forming N.sup.+ N.sup.- contacts to the N.sup.

Abstract: A method and apparatus for effecting a hermetic seal between an electronic component package and a package cover is disclosed. The method includes the steps of bonding a heater layer of conductive material to a sealing area of the package. A sealing material is then applied over a sealing area of the package cover. Optionally, a layer of sealing material may be applied over the conductive heater layer. The package and cover are contacted together and an electric current induced to flow within the conductive heater layer. The sealing material reacts to the heat caused by the electric current flowing in the heater layer, and bonds to the heater layer to effect a hermetic seal. Additionally, the seal can be intentionally broken by a reheating process to allow for repair or replacement of the electronic components contained within the package, and then resealed by the above described method.

Abstract: Method for packaging an expandable remote interface unit. The method includes providing a unit circuit board to which a plurality of expansion module interface boards may be detachably coupled without making a permanent connection. The unit circuit board and at least one expansion module interface boards are preferably housed in an enclosure which admits of easy disassembly, so that expansion module interface boards may be added or deleted without the need for soldered connections.