Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. For example, extracting the resistance from a straight section of interconnect wire may be performed by multiplying a known resistance per unit length by the length of the straight section of interconnect wire. For more complex extraction sub problems, machine learning is used to build models. In one embodiment, Support Vector Machines are constructed to extract the desired electrical characteristics.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a design layout. The region contains a plurality of nets and has multiple interconnect layers. The method identifies routes for a set of nets in the region, where some of the routes utilize vias to traverse multiple interconnect layers. The method then moves at least one via to improve the routing.

Abstract: For a path search that identifies a path between source and target states in a space, some embodiments of the invention provide a method for determining viability of an expansion of a path from a first state to a second dimensional state. The method computes a first cost function that expresses the cost of the path to reach the second state. The first cost function is defined over the second state. The method then determines whether the first cost function expresses a better cost over any portion of the second state than a second cost function that expresses the best cost of paths that have reached the second state during the path search. The expansion is a viable one if the first cost function expresses a better cost over at least a portion of the second state than the second cost function.

Abstract: Some embodiments of the invention provide a path-searching method. This method identifies two sets of states in a multi-state space, where at least some of the states have at least one dimension. It then performs an epsilon-optimal path search to identify an epsilon-optimal path between the two set of states. The epsilon-optimal path is a path that is within an epsilon of the optimal path between the two sets of states. During the espsilon optimal search, the method propagates a cost function that is defined over one state to another state.

Abstract: A routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.

Abstract: Some embodiments of the invention provide an integrated circuit (“IC”) design layout that includes topological routes. This layout includes several nets, each with a set of routable elements in the IC design-layout region. For each net, this layout also includes a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes. In some embodiments, the IC layout further includes a topological graph that represents the IC design layout topologically. The topological graph includes several topological items including a set of items for each net that represent the net's routable elements. Each net's topological route specifies an associated set of items in the topological graph.

Abstract: Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and retained to obtain a model that is smaller than the original netlist.

Abstract: The present invention relates generally to the field of design automation. More particularly, the present invention relates to a system and method for the modeling of circuit components for use by a simulator. The present invention includes a model of a circuit component having a plurality of properties that depend on at least two variables comprising: a space defined by the two or more variables; a partition of said space comprising a plurality of regions wherein at least two of the properties share said partition; and at least one definition representing at least one of the properties in at least one of the regions.

Abstract: The present invention introduces novel methods of performing integrated circuit layout extraction. In the system of the present invention, a complex extraction problem is first broken down into a set of smaller extraction sub problems. Some of the smaller extraction sub problems may be handled by simple parametric models. However, for the frequent complex extraction sub problems, machine learning is used to build models. Specifically, Support Vector Machines are constructed to extract the desired electrical characteristics. To build the Support Vector Machines, Experimental design is employed to select a set of training points that provide the best information. In one embodiment, the training point set is created by creating a critical input spanning set, adding training points from critical regions in the input space, and adding training points from frequently encountered profile cases.

Abstract: An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially processes the layout file to generate a separate database for each layer. Each database includes a separate table for each grid line on its corresponding layer, and each table includes a separate entry for each conductor residing along that grid line containing data indicating dimensions and a position of its corresponding conductor along that grid line. The tool processes the databases for each layer in ascending order to estimate capacitances between conductors on that layer and to generate set of data structures mapping the amount of conductor surface area on that layer to areas of layers above that layer, and to areas of layers below that layer in which conductors reside.

Abstract: A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.

Abstract: A method for modeling a substrate, which includes obtaining vertically discretized doping profiles in the substrate to facilitate modeling. The method includes employing substrate region names and substrate cross-section names as access keys to permit accessing of the vertically discretized doping profiles. The use of the combination of region names and substrate cross-section names as unique access keys simplifies access to doping profile information for modeling purposes and yields valuable information pertaining to the presence of p-type to n-type material transitions. The information pertaining to transitions may be employed to improve substrate modeling accuracy through the inclusion of junction capacitances with the modeling process.

Abstract: A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of each device. For each column and each row of cells having a plurality of device outlines contained completely therein, the position of one of the device outlines is determined and a constraint is established for each other device outline that expresses its position with respect to the position of the one device outline. A spacing constraint for each pair of adjacent device outlines is established that expresses a spacing therebetween. The foregoing constraints are solved simultaneously and a layout of the device outlines is generated in accordance with the solution.

Abstract: A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened representation; 2) generating a primitive database using the source file, where the primitive database includes a geometries-describing section for storing a plurality of primitive subcircuit blocks; 3) generating an instance database using the geometries-describing section, where the instances database includes instance subcircuit blocks corresponding to explicitly-expressed primitive subcircuit blocks with predefined geometric values; 4) generating a simulation database using the instance database, where the simulation database includes simulation subcircuit blocks corresponding to fully-flattened instance subcircuit blocks; and 5) simulating the circuit using the simulation database, the instance database, and the primitive database.

Abstract: A method for simulating a circuit includes representing the circuit as a hierarchically arranged set of branches, including a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that has one or more subcircuits and a second branch that has one or more subcircuits. The first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches, where a subcircuit at a higher hierarchical level includes one or more subcircuits in a lower hierarchical level.

Abstract: Described is a method for validating a digital design using a simulation process. All possible design states of the design are divided into a plurality of validation regions. In the simulation-process, the method records and updates the simulation history for each of t he validation region. When a particular stimulus is specified by the designer to perform a step of simulation for a current state within one of the validation regions, the process determines simulation efficiency by examining the specified stimulus and the simulation history of the validation region. The method may transform the specified stimulus into a more interesting stimulus to improve the efficiency and coverage of the simulation process.

Abstract: Some embodiments of the invention provide a method for propagating a first piecewise linear function (PLF), which is defined over a first state, to a second state, which is a line. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. For instance, in some embodiments, the space is a graph that includes points, lines, and surfaces. The method projects vectors from points on the first state that are locations of inflection points in the first PLF. At any intersection of the line and one of the vectors, the method computes a cost. The method also computes a cost at any endpoint of the line that does not intersect one of the vectors. Based on the computed costs, the method then specifies a second PLF that is defined over the second state.

Abstract: Some embodiments provide an LP method that identities routes. In some embodiments, this method is used by a router that defines routes for nets within a region of a design layout. Each net has a set of pins in the region. The method partitions the region into a set or sub-regions. For each particular net, the method identifies a set or route. Each route for a net traverses the sub-regions that contain the net's pins. Each route includes a set of route edge, and each route edge connects two sub-regions. Also, some of the identified routes have route edges that are at least partially diagonal. The method formulates a linear-programming (“LP”) problem based on the identified sets of routes for the nets. The method then solves the LP problem to identify one route for each net. In some embodiments, the formulated LP problem is an integer-linear-programming (“ILP”) problem, and solving the ILP problem returns integer solutions that specify one route for each net.

Abstract: The present invention introduces several methods for implementing arbitrary angle wiring layers for integrated circuit manufacture with simulated Euclidean wiring. Entire routing layers may be implemented with arbitrary angle preferred wiring using simulated Euclidean wiring. In a first embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and vertical interconnect wire segments. In another embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and diagonal interconnect wire segments.

Abstract: A method for simulating analog behavior of a circuit in a simulation system includes representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that has one or more subcircuits and a second branch that also has one or more subcircuits. The first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches.