Abstract: Some embodiments of the invention provide novel methods for representing items in a design layout. For instance, some embodiments use a method that represents an item in terms of n values that define n half-planes, which when intersected define the shape of the item. In some embodiments, n is a number greater than four. Some embodiments use a method that (1) identifies a first set of location data for the item with respect to a first coordinate system, (2) identifies a second set of location data for the item with respect to a second coordinate system, and (3) specifies the item in terms of the first and second set of location data. In some embodiments, both the first and second coordinate systems have first and second coordinate axes.

Abstract: A system and method for testing an integrated circuit having internal circuit blocks. Each of the internal circuit blocks may have its own test circuit block, referred to as a socket access port. The integrated circuit preferably includes a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) connected to a set of boundary-scan cells, and connected in a hierarchical fashion to the lower-level test circuit blocks. Each of the lower-level test control circuit blocks preferably comprises a socket access port controller, and test operation is transferred downward and upwards within said hierarchical structure by communicating from a test control circuit block to the test control circuit block at the immediately higher or immediately lower level in the hierarchical structure. Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.

Abstract: Method and apparatus for the synthesis of electronic circuits and, more particuarly, to the synthesis of analog circuitry and mixed digital and analog circuitry, and related to the reuse of circuit designer knowledge for the simulation of mixed analog and digital circuitry to determine data points and to curve fit the data points to determine a polynomial equation that closely approximates simulated circuit performance, and related to the parameterization of circuit features with respect to circuit performance.

Abstract: Required precision and information content of datapath signals are used to define functionally safe transformations on data flow graphs. These transformations reduce widths of datapath operators and edges and enhance the mergeability of operators. An algorithm for optimally balancing data flow graph topology to further reduce the data path widths and further enhance mergeability is combined with the above in an iterative algorithm for optimizing DFGs.

Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the net's pins. Based on the first set of sub-regions, the method identifies a first route that traverses a second set of sub-regions. The first and second sets of sub-regions have a particular relationship. Based on this particular relationship, the method identifies a second route from the first route, where the second route traverses the first set of sub-regions.

Abstract: An IC layout tool determines areas of an IC layout in which to provide power wire interconnection vias by first querying a “world” HV tree keeping track of power wires and other objects within the IC layout to determine areas of overlap between power wires residing on differing layers of the layout. The layout tool then creates a separate via HV tree identifying positions of “via boxes” residing on areas of each layer of the IC between overlapping power wires. The tool manipulates the data stored in the via HV tree to partition and merge adjacent via boxes residing on each layer as necessary to produce via boxes indicating positions of a set of unobstructed, rectangular areas of each layer of the layout in which vias may be placed to interconnect overlapping power wires. The IC layout tool then places vias in each rectangular area of each layer the via HV tree indicates is being occupied by via boxes.

Abstract: A method for displaying a schematic diagram of a circuit showing multiple time-frame signal values across storage elements includes identifying one or more time-frames in a circuit. The one or more time-frames are determined from a number of consecutive storage elements in a signal path in the circuit. The method also includes receiving a request to display signal values associated with a first storage element at a time-frame t. The method further includes displaying a first signal value carried on a first signal line coupled to an output of the first storage element at time-frame t and displaying a second signal value carried on a second signal line coupled to an input of the first storage element at time-frame t−1. In another embodiment, the method identifies any loops that are in the circuit. In a loop, a signal value comes from a gate at a time-frame and loops back to a loop-back gate at an earlier time-frame.

Abstract: A business-to-business application service provider includes an Internet website and webserver with EDA-on-demand solutions for system-on-a-chip designers. Such website allows electronic designs in hardware description language to be uploaded into a front-end EDA design environment. A behavioral model simulation tool hosted privately on the webserver tests and validates the design. Such tool executes only in the secure environment of the business-to-business application service provider. The validated solution is then downloaded back over the Internet for a pay-per-use fee to the customer, and in a form ready to be placed and routed by a back-end EDA tool. Such validated design solutions are also downloadable to others in exchange for other designs, or available in technology libraries. The intellectual property created can be re-used, sold, shared, exchanged, and otherwise distributed efficiently and easily from a central for-profit clearinghouse.

Abstract: A method for identifying, by way of a genetic algorithm, test points to be inserted in an integrated circuit (IC) chip to improve the testability of the IC is described. The algorithm is particularly well suited for large circuit designs (several million gates) because it allows to simultaneous insert multiple additional test points at critical locations of the IC to gain supplemental controlability and/or observability and thereby eliminating the drawbacks associated with the single test point approach. To further improve performance, cost function gradient techniques are applied to guide the selection of potential test points for consideration by the algorithm. Fault simulation of random patterns is used to more accurately distinguish between random pattern testable and random resistant faults, and to provide a more accurate set of initial probabilities for the cost function calculations.

Abstract: An integrated circuit (IC) layout process is organized into two phases. During the Phase 1 of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase 2 of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.

Abstract: A clock tree syntheses (CTS) tool designs a group of clock trees to be incorporated into an IC design for conveying separate clock signals to clock sinks within the IC with a predetermined maximum group skew. The tool initially generates a separate, independently balanced, first clock tree design for each clock tree and then processes each first clock tree design to estimate an average path delay of the clock signal it conveys to each sink. The CTS tool then selects, as a target path delay, a highest average delay from among average delays computed for all clock trees. Thereafter the CTS tool generates a separate second clock tree design for each clock tree that is balanced to limit a difference between the target path delay and an estimated delay to each sink to a value that ensures a group clock skew will reside within the predetermined maximum group skew.

Abstract: A system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips, and systems comprised of multiple integrated circuit chips. Test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. Non-care bits in the test vector data are filled with repetitive, repeating, or other background data sequences. The background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data. The recovery can use hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or software residing in the tester and operating while the test is performed.

Abstract: Method and system for recognizing the presence of a reference signal having M components. A signal s(t) is received that may contain a reference signal s(t;ref). An M×M covariance matrix of the M components of the received signal is formed, and M eigenvector solutions V=Vj and associated eigenvalue solutions &lgr;=&lgr;j (j=1, 2, . . . , M) of the matrix relation R·V=&lgr; V are determined. A subspace S′ of the space spanned, spanned by a selected subset of the vectors Vj′ (j′=1, . . . , N(s)) is formed, with N(s) a selected number that is ≦M. Product signals s(t)·Vj′(t) are formed and integrated over a selected time interval, t0≦t′≦t, to form estimation signals xj′(t) (j′=1, . . . , N(s)). The estimation signal xj′(t) and the reference signal s(t;ref) are used to determine a weighting coefficient wj′(t) (j′=1, . . .

Abstract: A system and method for simulating the noise characteristics of phase locked loops (PLL's) and other devices. Voltage Controlled Oscillator (VCO) transfer function and phase noise data is first imported for a particular circuit from a Radio Frequency (RF) simulator. The phase locked loop blocks in the circuit are converted to calibrated behavioral-level models. A combined analog/digital model is used to model the VCO, which in turn uses a pseudorandom signal generator for simulating VCO noise. Information about VCO periods is then written to a file or memory for post-processing, such as creating noise spectrum data and noise spectrum plots.

Abstract: System and method for detecting an unauthorized movement of a communications or meter device, such as a meter that monitors and communicates a measure of use of energy or some other metered quantity (electrical, gas, water, etc.), to prevent meter tampering or removal. A bolt, screw, nail or other attachment mechanism, used to attach the device to a selected stationary or movable object, is provided with a permanent magnet having a selected magnetic field direction that can be transverse to, a selected attachment mechanism direction (e.g., transverse to a bolt shaft direction). A field-activated magnetic switch, such as a reed switch or a Hall effect switch, having a selected switch direction is located near the permanent magnet.

Abstract: A practical definition for determining a required precision is provided and used to reduce the widths of operators and edges of data flow graphs. A bottom-up procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.

Abstract: A practical definition for determining an upper bound on information content is provided and used to reduce the widths of operators and edges of data flow graphs. A top down procedure for systematically pruning data flow graphs is described. The result is shown to enhance the mergeability of subgraphs and provide reduced data path widths. This may result in lower area, power requirements and other benefits as readily understood in the field of circuit design.

Abstract: The present invention introduces several methods for implementing non Manhattan routing systems for integrated circuit manufacture. In one embodiment, a non Manhattan routing system is implemented by memorizing where intersections between wiring pitch grids occur and connecting such intersections with vias. In another embodiment, a gridless non Manhattan routing systems may be implemented by adapting a gridless Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: A clock tree synthesizer alters a clock tree design to balance a clock tree receiving and distributing one or more clock signals to many clocked devices (“sinks”) within an integrated circuit, wherein the clock tree includes one or more crossover and reconvergence points at outputs of multiplexers receiving clock signals via different paths through the clock tree. The clock tree synthesizer balances the clock tree by first balancing the subtree downstream of each multiplexer and then representing the multiplexer and the subtree with a separate macro for each multiplexer input, each macro representing the path delay from the corresponding multiplexer input to the sinks receiving clock signal inputs via the subtree. When the clock tree includes crossover points, the macros split the clock tree into a separate tree for each clock signal.