Patents Assigned to Cadence Design Systems
  • Patent number: 6882965
    Abstract: A method for hierarchical specification and modeling of scheduling in system-level simulations. The invention addresses the specification aspect by introducing an explicit notion of a scheduler that must be designed as part of the system. A scheduler effectively represents a scheduling policy for an architectural resource. A scheduling policy governs how behaviors assigned to a resource, gain access and share the resource. The invention includes a general framework for modeling a scheduling policy, which includes a simple mechanism that covers many common cases. This framework is part of a Virtual Component Codesign (VCC) process, which is targeted at consumer embedded system design. Two orthogonal models, one of a scheduler and one of a schedulable, comprise the overall modeling of scheduling in the invention. The two models interact by sending messages to each other via a simple protocol.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: April 19, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventor: Christopher Hoover
  • Patent number: 6883154
    Abstract: Some embodiments provide an LP method that identifies route propagations. In some embodiments, this method is used by a router that hierarchically defines routes for nets within a region of a design layout. The router (1) partitions the region into a first set of sub-regions, and (2) for each particular net, identifies a route that traverses a set of the first-set sub-regions. In some embodiments, the invention's method partitions the first set of sub-regions into a second set of smaller sub-regions. It then identifies a plurality of propagation possibilities for propagating each route into the second set of smaller sub-regions of the first set sub-regions. The method next formulates a linear-programming (“LP”) problem based on the identified propagation possibilities. The method then solves the LP problem.
    Type: Grant
    Filed: January 5, 2002
    Date of Patent: April 19, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Oscar Buset
  • Patent number: 6883148
    Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: April 19, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 6880143
    Abstract: An IC design indicating positions of cells within an IC is processed to determine whether conductors residing above the cells block via access to an input/output (I/O) terminal on an upper surface of any of the cells. Each cell spans several contiguous via spaces in a horizontal direction with each via space being sufficiently wide in that direction to contain a via extending upward from any I/O terminal occupying that via space. For each cell having an I/O terminal requiring via access, a separate first data word corresponding to each I/O terminal of that cell is generated. Each bit of the first data word corresponds to a separate one of the via spaces spanned by the cell and indicates whether the I/O terminal corresponding to that first data word occupies that via space.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 12, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventor: Hongtao Yu
  • Patent number: 6880138
    Abstract: The present invention introduces novel methods of generating input vectors for machine learning system that will perform extraction. Experimental design is employed to select a set of training points that provide the best information. In one embodiment, a set of input vectors and output vectors are analyzed to determine a set of critical input parameters. Then, a spanning point generation program is used to generate a set of spanning points that cover the identified critical input space. The training point set then used to train a machine learning model.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: April 12, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Arindam Chatterjee
  • Patent number: 6879934
    Abstract: Some embodiments of the invention provide a method that computes an estimated distance between an external point and a set of points in a region. This method initially identifies a non-Manhattan polygon that encloses the set of points. It then identifies a distance between the external point and a point on the boundary or within the first non-Manhattan polygon. Finally, it uses the distance to identify the estimated distance.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: April 12, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Jonathan Frankle
  • Publication number: 20050076317
    Abstract: To estimate a distribution of voltages or currents in the layers of a multi-layer circuit, an exemplary current flow in each layer is discretized into a number of current vector elements and at least one scalar charge element related to the charge associated with each current vector element. A first distribution of voltages induced in each circuit layer is determined from current vector elements in all of the circuit layers. A second distribution of voltages induced in each circuit layer is determined from the scalar charge elements in all of the circuit layers. For each circuit layer, the first and second distributions of voltages induced therein are combined to determine an actual distribution of voltages in the circuit layer.
    Type: Application
    Filed: April 30, 2004
    Publication date: April 7, 2005
    Applicant: Cadence Design Systems, Inc.
    Inventors: Feng Ling, Vladimir Okhmatovski, Enis Dengi
  • Patent number: 6877146
    Abstract: One embodiment of the invention is a method of specifying routes for a group of nets. The method specifies a total cost. It then performs a first depth-first search to identify, for the group of nets, a complete routing solution that has a cost that does not exceed the total cost. A routing solution for a set of nets includes a route for each net in the set. If the search does not find the complete routing solution, the method then increments the total cost and performs a second depth-first search to identify a complete routing solution for the group of nets that has a cost that does not exceed the incremented total cost.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: April 5, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 6877149
    Abstract: Some embodiments provide a method of pre-computing routes for nets in a region of a circuit layout. The method initially defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a routing operation. The method then identifies a primary set of sub-regions that has more than one sub-region. It then determines whether the primary set of sub-regions is an open set that has a sub-region that is not adjacent to any other sub-region in the set. If the primary set of sub-regions is not an open set, the method identifies a route that connects the sub-regions in the primary set, and stores the identified route for the primary set of sub-regions.
    Type: Grant
    Filed: January 13, 2002
    Date of Patent: April 5, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Heng-Yi Chao
  • Patent number: 6877013
    Abstract: Geometric objects, such as polygons, are defined in a multi-dimensional data space, and are represented by data segments. “N” dimensional hierarchical trees, or “ng” trees, are generated to organize the data segments into “outside child nodes” and “inside child nodes” in accordance with a discriminator value. One of “n” sides of a polygon is selected as the discriminator value. To create the ng tree, data segments are designated as “outside child nodes” if a data segment is outside the plane defined by the discriminator value, and data segments are selected as “inside child nodes” if the data segment is inside the plane defined by the discriminator value. This process of partitioning data segments into inside child nodes, and outside child nodes is repeated recursively through each level of the ng tree. Techniques to represent diagonal interconnect lines of regions defined in a multidimensional design layout of an integrated circuit are disclosed.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: April 5, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tom Kronmiller, Steven Teig
  • Patent number: 6877143
    Abstract: A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: April 5, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert J Palermo, Karem A. Sakallah, Shekaripuram V. Venkatesh, Mohammad Mortazavi
  • Patent number: 6874133
    Abstract: A plurality of member devices is defined in a conformal outline having a pair of spaced parallel sides. Associated with each member device is a spacing constraint that sets a minimum distance the member device can be spaced from another member device and each side of the conformal outline. The spacing between member devices and/or the sides of the conformal outline are increased and/or decreased as necessary to minimize the area of the conformal outline that the member devices are received in with no violation of the spacing constraints while excluding from the conformal outline all or part of any nonmember devices defined therein.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: March 29, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Rob A. Rutenbar, Elias Fallon
  • Publication number: 20050066295
    Abstract: Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.
    Type: Application
    Filed: October 22, 2004
    Publication date: March 24, 2005
    Applicant: Cadence Design Systems, Inc.
    Inventors: Laurence Cooke, Kumar Venkatramani
  • Patent number: 6870255
    Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: March 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, David Overhauser, Akira Fujimura
  • Patent number: 6865726
    Abstract: An IC layout system compiles a hierarchical netlist describing an IC into a database having a separate record for each cell and each module of the IC. Each database record references a cell library entry describing the cell or module and indicates a hierarchical relationship between its corresponding cell or module and other IC cells or modules. The system initially processes the database to reduce the number of cell and module records by combining hierarchically related cells and modules into larger cluster cells. The system then processes the database and cell library to generate a trial layout of the IC which positions highly interconnected cells near one another without regard to the hierarchical nature of the design.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: March 8, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mitsuru Igusa, Wei-Lun Kao
  • Patent number: 6858939
    Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.
    Type: Grant
    Filed: June 3, 2001
    Date of Patent: February 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, David Overhauser, Akira Fujimura
  • Patent number: 6858928
    Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: February 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, David Overhauser, Akira Fujimura
  • Patent number: 6858935
    Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: February 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, David Overhauser, Akira Fujimura
  • Patent number: 6859916
    Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 22, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Andrew Caldwell
  • Patent number: 6857117
    Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: February 15, 2005
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Asmus Hetzel