Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins of circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: Some embodiments provide a method of pre-computing attributes of routes for nets in a region of a design layout. The pre-computed attributes are used by an electronic design automation application that partitions a design-layout region into a plurality of sub-region.

Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver.

Abstract: Some embodiments of the invention provide a method that pre-computes costs of placing circuit modules in regions of circuit layouts. The method defines a set of partitioning lines for partitioning the region into a plurality of sub-regions during a placement operation. For each set of potential sub-regions, the method identifies a connection graph that traverses the set of potential sub-regions. Some of the connection graphs have edges that are at least partially diagonal. The method then identifies an attribute of each identified connection graph. For each set of potential sub-regions, the method then stores the identified attribute of the connection graph that is identified for the set.

Abstract: Techniques for increasing flexibility in use of virtual component blocks include a method for hardening a foundation block, a pin-unscrambling methodology for semi-hardened virtual component blocks, and parameterizable virtual component blocks. A method for hardening a foundation block and utilizing it in a circuit design comprises the steps of defining a virtual component foundation block, hardening an interior region of the foundation block including at least the critical timing components such as the system bus. The foundation block has a “soft collar” for allowing interface parameters to be specified when the foundation block is incorporated into a circuit design. In addition, the foundation block may comprise an internal, hierarchical clocking scheme for even clock distribution and optimum performance. For example, all internal clock delays may be padded, except the longest one, so that the clock signal arrives at all relevant reference points within the foundation block at the same time.

Abstract: An integrated circuit has a metal layer that includes conductors to provide interconnectivity for components of the integrated circuit chip. The metal layer is divided into at least two sections, such that a first section has a preferred direction and the second section has a preferred wiring direction that is different from the first preferred direction. The first and second preferred directions on a single metal layer may consist of any direction. The metal layer may be divided into more than two sections, wherein each section has a preferred wiring direction. Wiring geometries for multi-level metal layers are also disclosed.

Abstract: Some embodiments of the invention provide a method for identifying locations of potential via between two layers of a design layout. The method identifies on one layer a first non-rectangular polygonal region for containing the via, and identifies on the other layer a second non-rectangular polygonal region for containing the via. It then determines whether an intersection of the first and second regions is sufficiently large to contain a via. If the intersection is sufficiently large, the method identifies the intersection of the two regions as a region for containing a via.

Abstract: Some embodiments of the invention provide a method for identifying topological routes in a multi-layer region of a design layout. The method selects a first net that has several routable elements. For the selected net, it then specifies a first multi-layer topological route that connects the first net's routable elements before selecting another net for routing. The first topological route traverses a plurality of layers. In addition, a topological route is a route that represents a set of diffeomorphic geometric routes.

Abstract: The present invention introduces several methods for laying out integrated circuit designs that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuit designs are laid out by creating an initial route and then compacting the design down. In another embodiment, gridless non Manhattan integrated circuits are laid out by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: A system for using machine learning based upon Bayesian inference using a hybrid monte carlo method to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, complex mathematical models are created using machine learning techniques for all of the smaller simpler extraction problems.

Abstract: Some embodiments of the invention provide a method for generating a route for a net in an integrated circuit (“IC”) layout. The method receives a previously defined route. From the received route, it generates several constraining points for specifying a geometric route that is based on a particular wiring model. The method then uses the constraining points to generate a geometric route that traverses diagonal and Manhattan directions.

Abstract: Some embodiments of the invention provide a method of costing routes for a set of nets. The method identifies at least one route for each net, where each route has a particular length. It also identifies an estimated route length for each net. It then computes a cost that includes an exponential expression for each net. Each net's exponential expression includes a base and an exponent. The exponent of each net's exponential expression includes the length of the net's route divided by the estimated route length for the net.

Abstract: Some embodiments of the invention provide a method of identifying routes for net in a region of a design layout. The method identifies a first route for a first net without using a routing grid. It then updates at least one previously defined route for another net to account for spacing constraints relating to the first route. In some embodiments, the method further (1) identifies previously defined routes that might need to be modified to account for spacing constraints relating to the first route; (2) examines the identified routes to determine whether the identified routes need to be modified to account for spacing constraints relating to the first route; and (3) updates several previously defined routes to account for spacing constraints relating to the first route.

Abstract: A pre-stored vector interrupt handling system for rapidly processing interrupt requests from input/output (I/O) devices in processor-based systems includes selection logic and an interrupt vector store to quickly deliver a branch instruction from the interrupt vector store directly to the execution unit of a processor. The interrupt vector store is either pre-loaded with a table of the processor's branch instructions during system initialization or implemented in ROM. During normal operation, when an interrupt is received, a master interrupt signal is issued to the processor, which asserts an instruction cycle mode signal to external chip select logic. The chip select logic deselects the program store and selects the interrupt vector store. An interrupt vector from the vector store is loaded onto the data bus and then directly into the execution unit of the processor.

Abstract: Some embodiments provide a method of propagating a first function, which is defined over a first state, to a second state in a multi-state space. The method identifies vectors to project from at least some points on the first state that serve as locations of inflection points in the first function; where the vectors are identified based on a model that allows penalizes measurements in certain directions more than other directions. Based on the projected vectors, the method then computes the second function from the first function.

Abstract: A system and method for protecting circuit designs from unauthorized use involves techniques for watermarking by embedding a hidden, recognizable input/output signature or code into the circuit design. An internal sequential function, such as a finite state machine, within the circuit design is used to generate a predictable output sequence when a known input sequence is applied. The free input configurations in the internal sequential function of the circuit design are identified and modified to generate the desired output sequence when the known input sequence is applied. A path among the free input configurations is selected, with output values in the desired output sequence being assigned the various state transitions. If there are not enough free input configurations to meet specified watermarking robustness criteria, then additional free input configurations may be added by, for example, adding one or more inputs, outputs or states to the finite state machine.

Abstract: The present invention presents optimization methods for interconnect geometries that readily extend to the UDSM region for determining on-chip interconnect process parameters more realistically and accurately than in the prior art. A method for reconstruction flow that re-assembles each of a number of optimized structures into one optimized interconnect process file, such as a process technology file for extractors. This optimized process technology file can use not only extracted interconnect process parameters but also the input of LPE (Layout Parasitic Extraction) tools in physical verification stage.

Abstract: Some embodiments of the invention provide a method of routing a set of nets. The method specifies a first order for the set of nets. It then routes the nets according to the specified first order. The method then specifies a second order for the set of nets, where the second order has the fewest possible number of differences with the first order. The method then routes the nets according to the specified second order.

Abstract: A hierarchical test control network for an integrated circuit includes a top-level test control circuit block having a chip access port (CAP) controller. The hierarchical test control network also has multiple lower-level test control circuit blocks connected to the top-level test control circuit block in a hierarchical structure. Each of the lower-level test control circuit blocks are a socket access port (SAP) controller. Test operation is transferred downward and upwards within said hierarchical structure.

Abstract: Some embodiments of the invention provide vias that are not in shape of quadrilaterals. In some embodiments, some or all vias are in shape of non-quadrilateral polygons, such as octagons and hexagons. In some embodiments, some or all vias have a circular shape. Some embodiments provide a first set of vias that have a diamond shape and a second set of vias that have a rectangular shape. In some embodiments, a via can also be formed by a diamond contact and a rectangular contact. The diamond contact has four sides. In the embodiments described below, all four sides of a diamond via contact have equal sides. However, in other embodiments, a via contact can be in shape of a diamond with a pair of sides that are longer than the other pair of sides. Similarly, in the embodiments described below, the rectangular via contacts are squares with four equal sides. However, in other embodiments, the length and width of a rectangular via contact can differ.