Abstract: A system for using machine-learning to create a model for performing integrated circuit layout extraction is disclosed. The system of the present invention has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. First, a complex extraction problem is decomposed into smaller simpler extraction problems. Then, each smaller extraction problem is then analyzed to identify a set of physical parameters that fully define the smaller extraction problem. Next, models are created using machine learning techniques for all of the smaller simpler extraction problems. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. The training sets are then used to train the models.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance effect from the approximated Manhattan wiring section may then be adjusted with a correction factor.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

Abstract: A method and system for obtaining information about electronic components, managing that information, and/or purchasing and procuring electronic components comprises a remote parts database connected to a distributed electronic network, such as the Internet. The remote parts database stores a plurality of dynamic parts for use in a schematic program run on a user workstation. When the user connects to the remote parts database, a listing of available dynamic parts are displayed on the user's workstation. The user selects dynamic parts for inclusion into an application (such as a schematic program) running on the user's workstation. The dynamic parts are downloaded to the user workstation and a local database. The downloaded information includes data regarding the parts functionality plus component data items such as supplier or distributor information, timing information, application notes, and a link (e.g., URL) to either the remote parts database or a remote supplier or manufacturer database.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: Some embodiments of the invention provide a method for pre-tabulating sub-networks. This method (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network in a storage structure based on the generated parameter. In some embodiments, the generated sub-network has several circuit elements. Also, in some embodiments, the generated sub-network performs a set of two or more functions. Some embodiments store each generated sub-network in an encoded manner. Some embodiments provide a method for producing a circuit description of a design. This method (1) selects a candidate sub-network from the design, (2) identifies an output function performed by the sub-network, (3) based on the identified output function, identifies a replacement sub-network from a storage structure that stores replacement sub-networks, and (4) replaces the selected candidate sub-network with the identified replacement sub-network in certain conditions.

Abstract: Some embodiments of the invention are placers that use lines that are not orthogonal with each other to calculate the costs of potential placement configurations. Some of these embodiments use non-orthogonal lines to measure congestion costs of potential placement configurations. For instance, some embodiments use non-orthogonal lines as cut lines that divide the IC layout into regions. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut lines.

Abstract: An abstraction mechanism is disclosed, which is capable of recognizing and abstracting precharged latches and flip-flops, and which is capable of generating a cycle ready representation of the precharged latches and flip-flops. In one embodiment, the abstraction mechanism abstracts precharged latches and flip-flops by using cofactors. In doing so, the abstraction mechanism accesses a logic level representation of a structure. Based upon the logic level representation, the abstraction mechanism derives one or more cofactors. These cofactors are then tested to determine whether they indicate precharge behavior, and whether they indicate latch or flip-flop behavior. If the cofactors indicate both precharge behavior and latch or flip-flop behavior, then the abstraction mechanism abstracts the structure as a precharged latch, or a precharged flip-flop, whichever is appropriate.

Abstract: This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.

Abstract: To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.

Abstract: A method and mechanism for performing improved performance analysis upon transaction level models. A system block may be modeled using transaction model at different levels of abstraction. A testbench may be used to apply a set of stimuli to a transaction model (e.g. a TLM model) and a RTL equivalent model, and store the resulting timing information into a database. The timing information stored in the database may be used to validate the performance of the transaction models and system block. The testbench may analyze transaction models in the TLM domain and the RTL domain through the employment of TVM (transaction verification models) which are components that maps the transaction-level requests made by a test stimulus generator to a detailed signal-level protocol on the RTL design.

Abstract: Static noise analysis simulates crosstalk functional noise by estimating a crosstalk functional noise window and by calculating the propagation of the noise window through a network. For example, the analysis can include simulations of injecting a noise window onto a network, propagating the noise window through the network until it reaches a register, and comparing the noise window with a register's sensitive window. The noise window for the net is calculated based on a duration of time in which noise glitches caused by capacitive coupling to aggressor nets can occur. The noise window is propagated through the net in a forward direction until the noise is attenuated or reaches a register's input. At the register's input, a sensitive window can filter the noise window so that only the portion of the noise window that coincides with the register's clock trigger time is considered in the noise analysis.

Abstract: Timing slack is allocated to edges of a timing graph by a converging loop that calls a Domain Restricted Timing Cone (DRTC) iterator. The DRTC iterator invokes a kernel program for each DRTC and computes time budgets for each edge. The time budgets are kept within established constraints of the corresponding DRTC. A timing verifier computes an amount of slack for each edge based on the time budget. An edge or arc of the timing graph is made permanent when the slack is less than a predetermined epsilon. The kernel program is based on any of a fast estimate, consideration of all time to end point (tte) and weight to endpoint (wte) pairs within the graph, and/or a set of tte wte pairs (or an envelope) that represent segments of a lowest slack to weight ratio.

Abstract: A Huffman algorithm is applied to revise the topology of a data flow graph. The result of the application of the algorithm is an increase in the sizes of at least some clusters (i.e., enhanced mergeability). The Huffman rebalancing of the topology may also result in the benefit of allowing further pruning of the bitwidths of data flow paths, which may further enhance mergeability. Thus, the algorithm may be applied with a maximum information content analysis.

Abstract: A system and method which allows for burst licensing, particularly for use in a circuit design and analysis system in which designers use tools to assist in characterizing and verifying the circuit. Burst licensing is used to provide licenses on an ‘as and when required’ basis to allow system users or customers to carry out massive parallelism of the simulation tasks when run from selected tools. When the system receives a request to start a task, the system checks-out a burst license for use in processing the task, and assigns the license to a particular CPU. The task is then performed at that CPU, and once completed the burst license is returned to the license pool.

Abstract: Some embodiments of the invention provide a method of generating a multi-layer topological path for a layout that has multiple layers. This method specifies a set of path expansions from a first topological item to a second topological item on a first layer of the layout. For a potential via expansion from the second topological item to a third topological item on a second layer of the layout, the method (1) identifies a first region on the first layer for the second topological item, (2) identifies a second region on the second layer the third topological item, (3) determines whether an intersection of the first and second regions is sufficiently large to contain a via, and (4) if the intersection is sufficiently large, adds the potential via expansion to the specified set of path expansions.

Abstract: One embodiment of the invention is a recursive partitioning method that places circuit elements in a IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots). For a net in the region, the method then identifies the set of sub-regions (i.e., the set of slots) that contain the circuit elements (e.g., the pins or circuit modules) of that net. The set of sub-regions for the net represents the net's configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the net's configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the net's circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

Abstract: The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a library to look up the corresponding noise tolerance parameter set values. In a variation, a set of formulae can provide the noise tolerance parameter set values. In an exemplary embodiment, the noise tolerance parameter set is taken to include the minimum peak value for the noise to be possibly harmful and the minimum width value for the noise to be possibly harmful.