Abstract: Two time budgeting techniques are provided that are suitable for early and late integrated circuit design phases, respectively. During the early design phase, both the positive and negative slack paths are time budgeted, such that a positive slack path cannot become a negative slack path after budget generation. If all the budget constraints are met by resynthesis for all circuit modules, then the technique guarantees that the final design, when assembled, meets all time constraints. During the late design phase, convergence is guaranteed. Further, synthesis runs for sub-modules focus initially on the worst critical path.

Abstract: A CAM cell design methodology and a method of pre-charge and comparison timing is disclosed. A CAM cell utilizing this design methodology includes a P-channel transistor configured to communicate a comparison result to a match line using the Miller effect. In one embodiment, the CAM cell further includes a positive comparison bit line, a negative comparison bit line, a first dual-ended CAM memory core cell configured to store data, a second dual-ended CAM memory core cell configured to store masking data, comparison circuitry, and a second P-channel transistor configured to communicate a masked state to the match line.

Abstract: A method is provided of optimizing a software program for a target processor in order to meet specific performance objectives and yet maintain portability, where the software program is initially coded in a high-level language. The method includes a first step of optimizing the software program in the high-level language, using optimizations that are substantially independent of the target processor to host the application. Preferably, if the performance objectives are met after the completion of this step, then the process preferably successfully terminates. However, if the performance objectives are not met, then the method preferably proceeds to a second step. In the second step, the initially optimized form of the software program is again optimized in the high-level language, although target processor-dependent optimizations are used. If the performance objectives are met after completing this second step, then the process preferably terminates.

Abstract: A general methodology for worst-case analysis of systems with discrete observable signals is disclosed. According to one embodiment, a signature &sgr; is chosen and a &sgr;-abstraction F is created, based on the system and the particular property to be analyzed. This procedure requires a user to facilitate the creation of an appropriate signature and &sgr;-abstraction. Next, for a given length of time T, a signature s is determined. From the signature s the worst-case boundary conditions are determined. The methodology may also be applied to timing analysis of embedded systems implemented on a single processor. The procedure calculates a time T which is an upper bound on the time a processor can be busy (i.e. busy period). Thus, for the busy-period analysis, the time T is no longer fixed. As in the first embodiment, a signature &sgr; is selected and a &sgr;-abstraction F is created. A workload function R is chosen, and a signature s and time T are calculated.

Abstract: A method used inside a static timing analyzer, or any timing-driven tool, to reduce the memory required to store the timing values. A static timing analyzer stores the arrival times and the required times at every pin of a digital circuit design. As circuit density increases, the number of pins increases proportionately. In order to be able to handle such large designs it is desirable to keep the memory requirement to a minimum, without compromising the performance. The technique presented herein produces significant memory requirement reduction for design with multiple clocks, or multi-cycle paths, with very little performance penalty. In a preferred embodiment of the invention, the method is carried out by the steps of: 1) Setting and propagating source triggering edges forward; 2) Determining target triggering; 3) Propagating the target triggering edges backward; 4) Determining the propagation bins; and 5) Finding a timing values translation function.

Abstract: Method and system for providing a signal with a controllable zero crossing time value. The system provides first and second two-sided triangular wave signals, identical but shifted by a selected fraction f·T of a period T of either triangular signal, and forms a weighted sum of the signals, weighted by A and 1−A, respectively, with 0≦A≦1. In each of two time regions within a period T, a zero crossing time of the sum varies linearly with choice of the value A.

Abstract: A system and method for generating inline subcircuits that enable a circuit designer to model and simulate circuits that when compared to conventional system and methods reduces the hierarchy from the perspective of the circuit designer, more efficiently models parasitic components, more efficiently parameterizes device models, more effectively creates models that are compatible with other simulation tools, can change the interface of a component without requiring the designer to use an extra layer of hierarchy, provides a more efficient interface by hiding details from the designer, enables hidden monitors and other functional designs to be automatically simulated by hiding these functions from the designer in a design level that is below the design level that is of interest to the designer, such as the geometrical parameter design level, can perform general purpose model binning with automatic selection, can export models and model parameters to other hierarchies without requiring an additional hierarchy in

Abstract: A gain adjustment circuit for maintaining the overall gain of a multi-component apparatus at a relatively constant level is disclosed. A multi-component apparatus in which the gain adjustment circuit may be implemented includes a first component and a second component. The first component has a variable gain, and receives as input a control signal which determines the gain of the component. The second component has an adjustable gain, and provides as output an output signal which affects the control signal fed to the first component. The gain adjustment circuit adjusts the adjustable gain of the second component based upon the control signal fed to the first component to maintain the overall gain of the components at a relatively constant level. More specifically, if the control signal is at a level which causes the variable gain of the first component to be high, then the gain adjustment circuit sets the adjustable gain of the second component to a low level.

Abstract: A method for selecting which covers to retain for each node reduces the computational burden for large logic cones and large cell libraries. At each node only K covers are retained. These covers have timing performances which are centered around the ideal timing performance for that node, and do not include inferior covers. The computational burden in selecting the covers for each node is based on the number K, and the number of inputs to that node.

Abstract: A computer-automated tool re-positions an instance relative to another instance along a given dimension. First, positions of both instances along the given dimension are determined. Then, a modified position is determined for one instance according to a convex function, which defines a global minimum solution between the initial instance positions.

Abstract: A method of creating multi-gate transistors with integrated circuit polygon compactors is disclosed. Specifically, in order to provide a more efficient layout when the size of a transistor is increased during design migration, a small multi-gate transistor is formed by inserting at least one parallel transistor over the diffusion layer of the target transistor, between a gate and contact. The compactor then enforces the new design rules, and adjusts the relative sizes of the parallel transistors as required. The resulting multi-gate transistor structure is much more compact than a single large transistor, providing a more efficient design layout.

Abstract: A method and system for generating reduced models of systems having a time-varying elements, a non-linear elements or both is provided. The system and method can be utilized with any systems that are capable of being described with non-linear or time-varying differential equations. The method and system are especially useful for automated extraction of reduced models for nonlinear RF blocks, such as mixers and filters, that have a near linear signal path but may contain strongly nonlinear time-varying components. The models have the accuracy of a transistor level nonlinear simulation but are very compact and so can be used in system level simulation and design.

Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: MOS Cascode amplifier circuits are subject to long-term or instantaneous changes (degradation) of performance characteristics by excess substrate currents. These currents can be generated in the grounded source transistor of the cascode connected output transistors during peak excursions of drain-source voltage across the grounded source transistor when the output voltage of the MOS Cascode amplifier circuit is at a maximum. An improved MOS Cascode amplifier circuit arrangement includes a voltage limiting bias circuit arrangement of additional transistors. The bias circuit arrangement acts as a series voltage-limiting device between the MOS Cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS Cascode amplifier circuit output voltage is at its maximum value.

Abstract: A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A method of Multi-slot Averaged Linear Interpolation (MALI) to estimate channel transfer characteristics at a receiver in a wireless network. The method and system are particularly well suited to use in wideband CDMA transmission systems. The steps of the method include calculating an instantaneous channel estimation from each slot in a transmitted signal, combining the instantaneous channel estimations for adjacent slot groups, and linearly interpolating between multi-slot averages to provide each symbol within a slot an accurate estimate of transfer characteristics for that symbol.

Abstract: According to a custom physical design process for integrated circuits, a method is provided for creating layouts characterized by optimal-length chains for different types of MOS circuit designs, including mixed-signal MOS designs. A chaining engine having a device library and operating on a computer converts a circuit representation such as a netlist file into a layout file characterized by optimal-length chains. Such conversion may be accomplished in linear time. From a circuit representation, a bipartite graph is prepared. A starting node in the bipartite graph is selected according to enumerated Euler trail algorithm rules. A constraint greedy walk is conducted to generate layout chains, and is preferably repeated until the bipartite graph is exhausted of edges, at which point the resulting layouts are returned. A single optimal layout solution can be obtained without enumerating all the possible layout options, resulting in a considerable speed advantage over conventional techniques.