Abstract: A method and apparatus for making electrical circuits having RLCG lines is disclosed. The method depicts a circuit element taper of a selected element type as dependent upon an accumulated circuit element quantity. The method matches projections of the circuit element taper with projections of an approximate taper. The approximate taper depends upon the accumulated circuit element quantity. At least one reduced quantity for circuit element quantities of the selected element type is obtained on the computer. The one reduced quantity can be arranged in a reduced RLCG line having approximately the same performance as the RLCG line. The present invention should be particularly useful in verifying timing specifications and during the making of integrated circuits.

Abstract: A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

Abstract: A voltage to current (V-I) converter includes a low pass filter, a first converting element, a second converting element, and an output. The low pass filter receives an input voltage signal and outputs a filtered voltage signal. The output of the low pass filter is fed to the first converting element, which converts the filtered voltage signal into a corresponding output current which is fed to the output of the V-I converter. Preferably, the voltage to current gain of the first converting element is high. The low pass filter and the first converting element form a low frequency or DC signal path. The V-I converter further includes a second converting element, which receives the input voltage signal and converts it into a corresponding output current which is also fed to the output of the V-I converter. This current is combined with the output current from the first converting element to produce an overall output current.

Abstract: Provided are a method, article of manufacture, and apparatus for matching candidate clusters to cells in a technology library. An automated design system comprises a computer configured to use second order signatures in generating candidate permutations of each permutation group in a canonical form of the candidate function. The system selects first and second symmetric subgroups, determines a second order signature for the candidate function and the first and second symmetric subgroups, and compares the second order signature to a corresponding second order signature for a library cell function. If the signatures match, the permutation is continued with the first and second symmetric subgroups being included in an intermediate permutation. If not, the system produces no more intermediate permutations beginning with the first and second symmetric subgroups. Further symmetric subgroups are added to the intermediate permutation.

Abstract: Provided are a method, article of manufacture, and apparatus for identifying candidate clusters for matching to cells in a technology library. An automated design system comprises a computer configured to extract a portion of a circuit, levelize it, select a first node, identify the realizable clusters at the inputs of the first node, and combine the first node with realizable clusters at the inputs to produce candidate clusters. A dummy cluster is used at each input to represent using the input as a fanin. The system takes the cross product of the sets, and the first node is merged with each element of the cross product to produce a set of candidate clusters. The candidate clusters are then checked for realizability by comparing them to cells in the technology library, which includes dummy cells to facilitate mapping to large cells in the technology library. A set of realizable clusters is produced for the first node.

Abstract: A method of making a phase lock loop circuit is disclosed. The method includes a method of simulating the phase lock loop circuit. The simulation runs on a system for making phase lock loop circuits. The simulation step initializes a reference frequency variable associated with a reference frequency of a phase lock loop circuit. The simulation method also initializes a voltage controlled oscillator (VCO) frequency variable associated with a VCO frequency of the phase lock loop circuit. A phase error is obtained from a frequency error between the reference frequency variable and the VCO frequency variable. The simulation method resets the phase error by a reset phase level when the phase error is approximately the same as a multiple of a reset threshold. When the frequency error changes sign, the phase error is permitted to also change sign. The simulation also determines a loop filter input for the phase lock loop circuit that depends upon the phase error and the frequency error.

Abstract: A Viterbi decoder generates a branch metric table from first and second data signals taken at two sample times and provides selected branch metrics to an add/compare/select circuit in response to branch indices from a branch index generator. The branch metrics in the branch metric table are the sixteen combinations of the sum of the first and second parallel data signals at first and second sample times and the inverse of such signals. The branch index generator generates the branch indices in response to a received state from the add/compare/select circuit, convolutional code polynomials and the possible states of a radix-4 trellis. The add/compare/select generates a survivor path decision based on the selected branch metrics.

Abstract: Efficient methods for verifying the timing behavior of a system in which various tasks are executed on a processor, and each task is enabled (i.e., becomes ready to execute) in response to the occurrence of an external event and/or the completion of another task. The methods are computationally efficient, requiring an execution time that is polynomial in the number of tasks in the system. The methods can be used in complementary fashion with more computationally intensive techniques for timing behavior verification, such as simulation or prototyping, by limiting the use of such techniques to those systems whose correctness is not proven by the methods.

Abstract: A method and apparatus simulates the performance of a system from a user-specified description of the components in the system and the interconnections between the components. The user may specify the descriptions using a consistent syntax. Conservation relations are automatically generated using the description of the components, the interconnections between the components in the system, or both. The description provided by the user and the conservation requirements generated may be translated into models for use by a conventional simulator to complete the simulation. Alternately the description and the conservation relation may be formulated into a set of relations and solved using conventional methods, such as Modified Nodal or Sparce Tableau. System performance simulation information is then generated as desired by a user.

Abstract: A method for determining the location of electric leaf cell circuits within the architecture of a semiconductor chip includes determination of the longest signal delays through an electric leaf cell circuit by evaluating independent channel connected components, reorganizing the circuit elements of each channel under evaluation into acyclic form, restructuring the acyclic form of channel connected components within the electric leaf cell circuits being structurally positioned in the chip architecture by selected reduction processes, determining input state vectors for each input and output pin connection pair of the electric leaf cell circuit in which an input pin connection state change is reflected in an output connection pin state change, and determining placement of the leaf cell within a semiconductor circuit module with reference to the greatest delay within each leaf cell.

Abstract: A computer-based system and method for efficiently identifying a new index bit sequence, utilizing a single technique to rearrange any size table, generating new index bit sequences without utilizing a significant amount of memory resources, and rearranging table entries only once. A mask array defines the new index bit sequence for a new table. The mask array has N entries of N bits each where N is equal to the number of bits in the old table index. The table entries in the old table to form a new table by initializing an old table index (OI) and a new table index (NI) and setting the new table entry associated with the NI equal to the old table entry associated with the OI. Then the new index that is associated with the next old index value by using the mask array to sequentially mask bits in the NI corresponding to mask bits in the mask array is dynamically generated.

Abstract: A method and apparatus simulates the performance of a system from a user-specified description of the components in the system and the interconnections between the components. The user may specify the descriptions using a consistent syntax. Conservation relations are automatically generated using the description of the components, the interconnections between the components in the system, or both. The description provided by the user and the conservation requirements generated may be translated into models for use by a conventional simulator to complete the simulation. Alternately the description and the conservation relation may be formulated into a set of relations and solved using conventional methods, such as Modified Nodal or Sparce Tableau. System performance simulation information is then generated as desired by a user.

Abstract: A computer system, method and software product enables automatic placement and routing of datapath functions using a design methodology that preserves hiearchical and structural regularity in top down designs for datapaths. The system includes a datapath floorplanner, a datapath placer, and routing space estimator. The datapath floorplanner allows the designer to establish and maintain during floorplannning operations datapath regions that include a number of datapath functions each. The datapath floorplanner creates the datapath regions from a netlist specifying logic cell instances and connectivity information, and from a plurality of tile files. A tile file is a structured description of a datapath function, describing the relative vertical and horizontal placement of all logic cell instances within the datapath function. There is one tile file for each unique datapath function. The datapath function instances then are associated with a particular tile file by the tile file list file.

Abstract: A system and method for testing the placement of logic circuits on a regularly repeated array of integrated devices includes a base array memory, a basis memory, a floor plan memory, an array class memory, a logic cell index memory, a legal location index map memory, a legal location table memory and an engine. The system creates an array class for each type of device that is fabricated on the base array. The engine then tests each location of a basis of each array class for the legality of placing each logic cell of an associated group at that location. The engine then constructs a map of the array class, the legal location index map. Each entry on the map corresponds to a location in the array class, and each entry on the map contains a reference to a bit pattern. The engine also constructs a legal location table. The legal location table is a set of unique bit patterns that indicate the logic cells that may be placed at a location.

Abstract: A method and apparatus simulates the performance of a system from a user-specified description of the components in the system and the interconnections between the components. The user may specify the descriptions using a consistent syntax. Conservation relations are automatically generated using the description of the components, the interconnections between the components in the system, or both. The description provided by the user and the conservation requirements generated may be translated into models for use by a conventional simulator to complete the simulation. Alternately the description and the conservation relation may be formulated into a set of relations and solved using conventional methods, such as Modified Nodal or Sparce Tableau. System performance simulation information is then generated as desired by a user.

Abstract: A method implemented on a computer system for enhancing performance of an integrated circuit design verification system, the computer system having a memory including a circuit design, the circuit design including a base layer, a first layer, a second layer, a first derived layer, and a second derived layer, the first derived layer defined in response to operation between the base layer and the first layer, the second derived layer defined in response to an operation between the second layer and the first derived layer, includes the steps of retrieving the first layer from the memory, the first layer located within the base layer, deriving a negative first derived layer in response to the first layer, the negative first derived layer being a negative domain representation of the first derived layer, and verifying the circuit design in response to the negative first derived layer.

Abstract: A computer-based system and method for efficiently identifying inverted bits in an address, utilizing a single technique to rearrange any size table, generating new index bit sequences based upon inverted index bits without utilizing a significant amount of memory resources, and rearranging table entries only once. The present invention utilizes a mask that defines the address bits that are inverted for a new table. The present invention then rearranges the table entries in the old table to form a new table. Once generated the new table can be used in place of the old table thereby requiring no more memory than the old table. Accordingly, the present invention provides a system and method for identifying the index bits to be inverted after the lookup table and computer program have been generated while utilizing significantly less memory than conventional systems and methods.

Abstract: A method for performing a hierarchial timing driven layout of a circuit based upon gate-level design data and circuit timing constraints, the circuit including a plurality of cells, includes: partitioning the plurality of cells into a plurality of logical blocks, a first logical block including a first plurality of cells; budgeting a block timing constraint for each of the plurality of logical blocks in response to the gate-level design data, to the circuit timing constraints, and to the partitioning of the plurality of cells into the plurality of logical blocks; placing the plurality of logical blocks within a circuit floorplan, each logical block associated with a block location within the circuit floorplan; rebudgeting the block timing constraint for at least one of the plurality of logical blocks in response to the placement of the plurality of logical blocks within the circuit floorplan; placing the first plurality of cells within a block location associated with the first logical block; and rebudgeting

Abstract: A method for generating a physical integrated circuit layout, using the similarity between a template and the physical layout as a metric. This automated template-driven layout methodology creates a physical integrated circuit layout which approximates the specified template as closely as practicably possible. The similarity of the positioning of circuit elements in a physical layout is improved with regard to the positioning of those same circuit elements in a template. The circuit elements' placement is incrementally improved by attaching a cost to each placement, with a lower cost reflecting a better match between circuit element placement in the physical layout and the template. Fuzzy logic concepts are employed to determine the cost of a given layout.

Abstract: A system and method increases discrete function simulator performance by creating a data structure that completely and accurately models a system of discrete function elements. A discrete function simulator simulates the system using the data structure. Sequential circuits are converted into blocks of combinational elements having latch variables stored to and read from memory. The simulator performance is dependent upon the number of system inputs and outputs and not on the number of discrete function elements in the circuit being simulated.