Abstract: A method and system for combinational verification tightly integrates multiple verification methods. The present invention performs random simulation on the inputs of two combinational netlists. The nets within the netlists are described as BDDs and divided into classes of cutpoint candidates based upon the signatures produced by the random simulation. Cutpoint candidates within each class are resolved to determine whether the candidates are equivalent. If the nets are likely to be equivalent, BDD composition is performed on the nets. Otherwise, SAT-based analysis is performed on the nets. If either method fails to resolve the cutpoints within an allocated amount of time or resources, then the other method is invoked and information learned by the first method is passed to the second method to assist in the resolution. This process repeats until the cutpoint candidates are resolved.

Abstract: A method of compressing a block of time series data involves sorting the data by variable name, separating the series of time values from the series of variable values, and performing data extraction and/or compression independently on the series of time values and on the series of variable values. The reduced volume of data is then written to a database. In a preferred embodiment, the time series of data represents data generated from a computer simulation of an integrated circuit. In order to efficiently compress the time series data, individual blocks of time series data representing a particular time range are sorted by variable name, with each variable name having associated time values and variable values. The time values and variable values are separated into two distinct data sets, and data compression is performed separately on the two distinct data sets. The compressed information related to each individual variable is then stored in individual variable blocks.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A technique for constructing a balanced H-Tree clock layout suited for application to clock signals in integrated circuits, but applicable to other signals requiring balanced distribution over a wide area, involves routing clock wires in a circuit design wherein internal circuit blocks are divided, to the extent possible, into groups having an equal number of circuit blocks. An upper H-Tree clock layout structure is established using the center of mass of each of the circuit block groups as guideposts. Adjustments in wire length to balance the wires of the H-Tree layout. A lower H-Tree clock layout structure is established using center points between pairs of adjacent or nearby circuit blocks as guideposts for the endpoints of clock wires, and then routing, to the extent necessary, wire segments to the individual circuit blocks.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.

Abstract: An integrated circuit design is divided into partitions which each contain two stages of information. The first stage corresponds to sources within the design, and the second stage corresponds to targets within the design. In one implementation, all of the sources in each partition are triggered by a common clock edge. In another implementation, all targets of each partition are triggered by a common clock edge. Specifying timing constraints in partitions can provide an efficient method of determining how much slack, if any, is present in the timing of a design.

Abstract: A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of simulation results. A transaction is defined as a specific sequence of transitions on a selection or grouping of signals over a period of time where the signal activity has some higher level operational meaning. Simulation results are recorded on a transaction basis by storing standard simulation results information along with transaction-specific data elements, including the name of the transaction, the start time of the transaction, the end time of the transaction, and the interface on which the transaction takes place. Additional transaction-specific data elements may include parent and child relationships and predecessor and successor relationships between transactions.

Abstract: A method and system of latch mapping for performing combinational equivalence checking on a specification and an implementation of a circuit that does not depend on signal names or circuit structure to determine the latch mapping. First, every latch is mapped to every other latch. Then, the resulting mapping is refined until it is semi-inductive. The refinement is performed by randomly producing a state that satisfies the mapping and applying a random input vector to the circuits. The resulting mappings are iteratively compared and new input vectors are applied to the circuits until the greatest fixed point of the refinement is found. Then, it is determined whether the greatest fixed point of refinement forces output equality. If the greatest fixed point does not force output equality, then a bug in a combinational block of the implementation is localized through an interactive procedure. If the greatest fixed point does force output equality, then it is determined whether it also satisfies a reset condition.

Abstract: A method and apparatus are provided for transitioning a power converter between a switched mode of operation and a linear regulator mode of operation. The power converter operates according to one or more intermediate modes of operation in which the switched mode and linear regulator modes cooperate to produce a shared power converter output. The power converter transitions between the various modes of operation in response to changes in circuit parametric conditions as defined by a series of state transition diagrams. Power converter output voltage is maintained in regulation during all modes of operation and transitions therebetween. The method and apparatus includes an integrated device that may be operated as a switch or a variable resistance device.

Abstract: A low-power controller for a discontinuous switched mode power converter. The controller has an inductor current sensing circuit to measure the inductor current flowing through an inductive charge storage element as well as an output voltage sensing circuit to monitor output voltage. The controller monitors both the converter output voltage and the inductor current and uses this information to modulate a peak inductor current trip point and controller switching frequency according to a control law curve in order to regulate converter output voltage. The controller prevents the switching frequency from falling below a predetermined minimum frequency. The control law curve is selectable to specify controller operation according to a desired combination of minimum switching frequency and maximum peak inductor current.

Abstract: A behavioral model for mixed signal RF circuits. The model approximates non-linear filtering effects for base-band (i.e. suppressed carrier) end-to-end systems analysis. The new model, the K-model, is a linear MIMO (multi-input-multi-output) model with output radius corrected by a non-linear SISO (single-input-single output) model and output angle corrected by a non-linear rotation. The SISO model uses a multi-tanh structure to synthesize a non-linear filter. The multi-tanh structure simulates non-linear behavior by gently switching between transfer functions as the base-band input varies. For excursions well into the steady state non-linear region of operation the K-model simulates large-signal base-band transients to within about 10 percent of those simulated with detailed unsuppressed-carrier models.

Abstract: A method and apparatus for managing simulation results involve identifying errors within a group of simulation results so that the errors can be recorded into a database and viewed for analysis. In a preferred embodiment of the invention, distinct transactions within a group of simulation results are identified and recorded along with the identified errors. Recorded error-specific data and transaction-specific data are then utilized to graphically display the simulation results such that individual transactions identified within the simulation results are graphically distinct and such that errors occurring during a transaction are visually identified with the transaction. Recording and displaying error information and raising the level of abstraction of simulation results from cycles and signals to transactions enables easier simulation analysis and debugging.

Abstract: A computer implemented, graph based method for determining the orientation of objects which can assume a plurality of orientations relative to a default orientation, including being rotated 90.degree. clockwise, mirrored about an X axis, or mirrored about a Y axis, where the X axis and the Y axis are orthogonal to each other, and having a plurality of orientation constraints, including a fixed orientation constraint which requires an object to have one of eight predefined orientations, a same orientation constraint which requires that every object in a set of two or more objects must have the same orientation, a mirrored orientation constraint, which requires that a pair of objects have a mirrored orientation about the X axis or the Y axis, and a same or mirrored orientation constraint, which requires that every object in a set of two or more objects must have either the same orientation or the mirrored orientation.

Abstract: Described is an one bit matched filter for generating a sequences of correlations between a signal bit stream and a sample stream of n sample bits. The n sample bits are arranged in a rang of n bit positions n, n-1, . . . , 2, 1. Among the n sample bits, m boundary positions are defined based on the bit pattern of the sample stream, where m<n. At a specific time T(k), the m boundary positions are used to generate a Contribution (k) for a section of signal bits that are shifted into the n bit positions. At the time T(k), a Correlation (k) is generated by adding the Contribution (k) with the Correlation (k-1) that was generated at the previous time T(k-1).

Abstract: An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

Abstract: In some embodiments, a light bulb for an electrodeless discharge lamp has a protuberance such that the cold spot of the bulb is located in the protuberance. The protuberance is spaced from the induction coil of the lamp so as to be easily accessible. Hence the cold spot temperature is easy to measure and control. In some embodiments, heat sinks are provided to cool the light bulb. An active control element including a Peltier element is provided to control the cold spot temperature.

Abstract: A charge pump having an automatic compensation capability comprises a current source and a current sink. The current source is selectively coupled to the output of the charge pump by a sourcing control. The sourcing control receives an input control signal and responds by controlling the sourcing current flowed from the current source to the output. Likewise, the current sink is selectively coupled to the output of the charge pump by a sinking control. The sinking control receives a second input control signal and responds by controlling the sinking current flowed from the output to the current sink. The charge pump further comprises a sensing circuit and a compensating circuit. The sensing circuit determines whether, given substantially identical input control signals, there is a difference between the sourcing current and the sinking current generated by the charge pump. If so, the sensing circuit provides at its output an indication of the current difference.

Abstract: According to the invention, a method for valuing the contribution of IP Blocks into integrated circuit (IC) designs includes implementing a novel concept for valuing technical and economic factors. Based upon such factors, users can more reliably value, select and use IP Blocks for their IC design that furthers their objectives. In an embodiment according to the present invention, a method for determining a group of IP Blocks from a plurality of IP Blocks to incorporate into a circuit design includes the steps of determining a circuit architecture to be implemented by the circuit design, and determining a valuation for implementing the circuit architecture.