Abstract: In one embodiment of the invention, a method for verification of an integrated circuit design is disclosed. The method includes independently executing simulation runs in response to a plurality of coverage models to respectively generate a plurality of coverage data for a plurality of functional blocks within one or more integrated circuit designs; generating a target coverage model to selectively merge at least first coverage data associated with a first coverage model and second coverage data associated with a second coverage model; and in response to the target coverage model and the plurality of simulation runs, selectively projecting the plurality of coverage data into a merged coverage data result associated with the target coverage model. The method may further store the merged coverage data results into a storage device. The plurality of simulation runs may include at least one functional simulation run and at least one formal verification run.

Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.

Abstract: Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as “suspicious”. The result of this process may be a list of suspicious inputs and a shorter and simpler test that still fails. The shorter test may be rerun and fields of the inputs recorded. New tests may be created with mutated fields. Mutated fields that result in passing tests may be considered suspicious fields. Suspicious inputs and fields may be presented to a user as part of an electronic design process.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for shapes on routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: Various embodiments of the present invention relate to bi-directional communication between an Integrated Circuit (IC) layout editor and various generic layout and/or pattern data viewers. Further, the present invention provides a bi-directional control between the IC layout editor and the various generic layout and/or pattern data viewers and allows substantially simultaneous display of an IC design in various IC mask layout data formats. The IC layout editor and the various generic layout and/or pattern data viewers include various tools. The bi-directional communication connects these tools to form connected tools. Subsequently, the actions performed by a connected tool in response to user interactions are synchronized with the actions performed by other connected tools.

Abstract: A method and system are provided for automatically generating executable system-level tests from an initial action or partially specified scenario by accumulating necessary complement actions and forming a set of constraints required by the initial action and the necessary complement actions. The set of constraints is solved by a constraint solving engine to provide an at least partial sequence of the actions and parameters thereto that satisfies the set of constraints. The sequence of actions that comply with the set of constraints are used to generate an executable system-level test code.

Abstract: Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

Abstract: An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically expandable nodes for constraint violations in a browser.

Abstract: Systems and methods for simulating and verifying a design are contemplated. Various embodiments determine a set of verification rules for a design, wherein the verification rules use a PSL or SVA syntax in a SPICE netlist to describ a property of the circuit design. The state of a circuit at a simulated first time, t1, can be determined. The state at the first time, t1, may be analyzed to determine if a triggering event has occurred. Based on the occurrence of the triggering event, the systems and methods can verify the state at the first time, t1, against the set of verification rules. Some embodiments of the systems and methods described herein can include a mixed-signal circuit including an analog portion and a digital portion, and the analog portion, the mixed-signal portion, or both, may be simulated and verified.

Abstract: A method and an apparatus to provide machine-assisted training have been disclosed. In one embodiment, the method includes monitoring action performed by a trainee during machine-assisted training and dynamically adjusting the machine-assisted training in response to the trainee's action. Other embodiments have been claimed and described.

Abstract: A method and system for randomizing memory in a functional verification test of a user design is disclosed. A random number is generated during the functional verification test. The data stored in the memory of the user design is stored. Encryption keys unique for each memory address of the memory are generated. Each encryption key for each memory address is a function of the random number and the memory address. Data in each memory address of the memory is encrypted with the encryption keys unique for each memory address. After exiting a low-power or power-off state, data in each memory address is read and decrypted using the same encryption keys. Data before and after the low-power or power-off state are compared to test memory loss.

Abstract: Disclosed is an improved method, system, and computer program product for performing core placement when presented with an I/O ring design. A multi-pass approach is taken to place and shape core objects into the available core area formed by the inner surface of the I/O ring. The multi-pass approach permits very fast placement of the core objects, which still provides for an accurate estimation of the die size and configuration requirements for the electronic design. Moreover, the present approach allows core objects to be placed in a way that retains any preferred affinities for the objects to be located near other objects, e.g., near specific I/Os on the I/O ring.

Abstract: Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions.

Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.

Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.

Abstract: A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and to achieve synchronization between the processor and any external device including other processors. These interfaces can also be used to achieve data transfer at the rate of one data element per interface in every clock cycle. This technique makes it possible to design multiprocessor SOC systems with high-speed data transfer between processors without using the memory subsystem. Such a system and design methodology offers a complete shift from the standard bus-based architecture and allows designers to treat processors more like true computational units, so that designers can more effectively utilize programmable solutions rather than design dedicated hardware.

Abstract: Disclosed are methods, systems, and articles of manufacture for processing a electronic design, which use a computer system to identify an operation associated with a task to be performed on the electronic design, to generate a hierarchical output for multiple shapes for performing the task based at least in part on performing an operation associated with the task, and to display or to store the hierarchical output. The task comprises a dummy fill insertion task or a design verification task in some embodiments. The methods or the systems may further determine or identify an inverse transform and apply the inverse transform to a shape before adding the shape to the hierarchical output. In some embodiments, there exists no duplication among the shapes in the hierarchical output.

Abstract: Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design.