Abstract: Methods, systems, and devices for logic synthesis that preserve a reset behavior of a circuit are provided. A method for logic synthesis may include providing the circuit. A memory element may be identified at a first location within the circuit, where the memory element is reset with a first reset value. The memory element may be relocated across a first portion of the circuit resulting in a one relocated memory element. The relocated memory element may be duplicated. The relocated memory element and the duplicated memory element may be connected with the circuit. Multiple reset values for the relocated memory element and the duplicated memory element may be determined, where the first reset value is produced at the first location when the multiple reset values are propagated through the circuit from the relocated memory element and the duplicated memory element to the first location.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: An invention is provided for improving performance in block based non-volatile memory when performing random small write operations. When requests for small page updates are received for a memory page currently storing data, the updated page data is written to a reserve memory page. The reserve memory page can be in the same memory block as the target memory page, or in an associated reserve memory block. In addition, the associated logical page address is temporarily remapped to the reserve page. Later, when time permits, the page data for the block can be reorganized into continuous pages in a new block.

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract: Graphical viewing of shapes and descriptive information in displayed graphical images. In one aspect, shape information is displayed in a graphical interface using a computer system and includes causing a display of an image on a display device with or more shapes, and causing a display of multiple labels on the display device. Each of the labels is associated with a different one of the displayed shapes, and the labels are derived from stored connectivity information for the one or more shapes describing the connections of the shapes.

Abstract: A system for dynamically representing repetitive loads of a circuit during simulation includes a simulator module having one or more computer programs for 1) identifying one or more driver circuits for driving a plurality of repetitive receiver circuits, where each driver circuit has an output port and each repetitive receiver circuit has an input port, 2) creating a branch node driver for connecting the input ports of the plurality of repetitive receiver circuits and the output ports of the one or more driver circuits, 3) creating a shared load for representing aggregated input port loads of the plurality of receiver circuits having a substantially same isomorphic behavior, 4) creating a port connectivity interface for communicating changes of signal conditions between the output ports of the one or more driver circuits and the corresponding input ports of the plurality of repetitive receiver circuits, and 5) simulating the one or more driver circuits and the plurality of repetitive receiver circuits in acco

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.

Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.

Abstract: Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern.

Abstract: Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems.

Abstract: An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving clock domain operating with a receiving clock signal. The invention includes determining a phase shift relationship between the source clock signal and a signal. When the phase shift relationship is below a predetermined threshold the data is transferred between the source clock domain and the receiving clock domain using a first plurality of stage operations. When the phase shift relationship is above the predetermined threshold, the data is transferred between the source clock domain and the receiving clock domain using a second plurality of stage operations that delay data transfer an additional half period of the source clock signal.

Abstract: A graphical editor displays graphical representations of underlying data items in a distribution of information-bearing states across a bounded region of a display. One or more of the data items are selected as belonging to a context of a user task or operation. The information-bearing states are redistributed in the bounded region of the display so that an amount of information sufficient to the task is provided through the graphical representations of the data items in the context and any space in the bounded region of the display needed to display such information is acquired by a decrease in the amount of information provided by the data items outside the context.

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.

Abstract: An electronic design automation (EDA) tool to validate representations of a design is disclosed. Reference and compared representations of the design are intended to respond to stimulus in the same way, but at different levels of abstraction. The reference and compared representations are simulated, at some point, to each generate waveform signals and measured results. Simulation can be with the same tool or different tools. The same or different testbench can be used on the reference and compared representations in the simulation. A design representation validation function compares the two sets of generated waveform signals and compares the two sets of measured results to identify any violations. The measured results and/or waveform signals could be loaded from previous simulations and just validated within the validation tool.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: Methods, systems, and machine-readable storage medium for logic synthesis that adjust a timing model of a circuit are provided. A first memory element from multiple memory elements of the circuit may be determined, where the first memory element is connected with a first portion of the circuit and is controlled by at least one first control signal. A combinational element within the first portion of the circuit may be determined. The combinational element may include at least one input or output coupled with a second memory element. The second memory element may be controlled by at least one second control signal. The second control signal may be incompatible with the first control signal. A first timing element may be inserted into the circuit at a location connecting the first timing element with the combinational element. A synthesis optimization may be performed utilizing the at least one first timing element.

Abstract: According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

Abstract: The present invention provides systems and methods for simulating an analog and mixed-signal circuit design comprising an analog circuit segment and a transmission gate network of a digital circuit segment, where the analog circuit segment is connected to the transmission gate network using a bi-directional connect module, where the analog circuit segment contributes with its own driving force to the digital circuit segment as an equivalent to a driver, and where the digital circuit segment contributes with its own driving force to the analog circuit segment. Additionally, in some systems and methods of the current invention, the bi-directional connect module defers to the transmission gate network any resolution of digital logic values to analog voltages, and any resolution of analog voltages to digital logic values.