Patents Assigned to Cadence Design Systems
  • Patent number: 8418094
    Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method loads the full design database information on the master; distributes the tasks to be processed in parallel; loads a full design on a master; spawns a plurality of slave sessions; sends to at least one slave a nutshell representation of the electronic circuit design; identifies a task to perform in parallel and sends the task to be performed in parallel; and receives execution results or processing results from some of the plurality of slaves and updates one or more databases to incorporate the execution or processing results. In some embodiments, the method allows speeding up the applications without major rewrite without a need for design partition, and without memory penalty.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: April 9, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnaud Pedenon, Philippe Lenoble, Claire Nauts
  • Patent number: 8418101
    Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 9, 2013
    Assignee: Cadence Designs Systems, Inc.
    Inventors: Andreas Kuehlmann, Xiaoqun Du
  • Patent number: 8413087
    Abstract: Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 2, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Guruprasad G. Rao, Mark Hahn, Laurent Volpe
  • Patent number: 8413093
    Abstract: Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: April 2, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Guruprasad G. Rao, Mark Hahn, Laurent Volpe
  • Patent number: 8413090
    Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 2, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andreas Kuehlmann, Xiaoqun Du
  • Patent number: 8413088
    Abstract: A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: April 2, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank Armbruster, Sandeep Pagey, F. Erich Marschner, Dan Leibovich, Alok Jain, Axel Scherer, Yaron Peri-Glass
  • Publication number: 20130080126
    Abstract: An apparatus and method for performing periodic noise (Pnoise) simulation with full spectrum accuracy is disclosed herein. Noise contributions of a circuit under consideration are identified and separated for different computation treatment. The different computation treatment results in computational efficiency without sacrificing accuracy of simulation results.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Applicant: Cadence Design Systems, Inc.
    Inventors: Xiaolue Lai, Yu Zhu
  • Patent number: 8407627
    Abstract: A method for inspecting lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to inspect a mask.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Robert C. Pack, Louis K. Scheffer
  • Patent number: 8407630
    Abstract: A method and apparatus for modeling and cross correlation of design predicted criticalities include a feedback loop where information from the manufacturing process is provided to cross correlation engine for optimization of semiconductor manufacturing. The information may include parametric information, functional information, and hot spots determination. The sharing of information allows for design intent to be reflected in manufacturing metrology space; thus, allowing for more intelligent metrology and reduces cycle time.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kevin Chan, Emmanuel Drege, Nickhil Jakatdar, Svetlana Litvintseva, Mark A. Miller, Francis Raquel
  • Patent number: 8407635
    Abstract: A method of producing a hierarchical power information structure for a circuit design, the method comprising traversing a circuit design hierarchy from a top design level to a bottom design level to identify any intermediate design levels, associating identified power nets with ground nets to produce one or more power domains, producing one or more power domains using the identified power nets and ground nets, identifying an instance of one or more special cells that are associated with a power related property and creating constructs for the special cells in the hierarchical power information structure, generating power rules for the intermediate level design using the special cell constructs, mapping higher design level power domains to lower design level power domains within the intermediate design level, and storing the power domains and power rules as power intent within an information structure associated with a schematic for the intermediate level design.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Amit Chopra
  • Patent number: 8407277
    Abstract: A full subtractor cell is disclosed including an XNOR gate having first and second inputs coupled to first and second bits; an XOR gate having first and second inputs coupled to an XNOR gate output and a carry input bit; a first AND gate having first and second inputs coupled to an XNOR gate output and the carry input bit; an inverter gate having an input coupled to the second bit to generate a complemented second bit; a second AND gate having first and second inputs coupled to the first bit and an inverter output to receive the complemented second bit; and an OR gate having first and second inputs coupled to a first AND gate output and a second AND gate output. An XOR gate output and an OR gate output generate the sum output bit and the carry output bit.
    Type: Grant
    Filed: October 26, 2008
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sabyasachi Das
  • Patent number: 8407228
    Abstract: Disclosed is an improved approach for managing, tracking, and querying hierarchical data in layouts. According to some aspects, hierarchical grids are employed utilizing a scheme that organizes physical objects into a set of gradually refined grids that avoids the need to maintain duplicates while enhancing the desirable characteristics of existing schemes, including fast query times, fast data structure initialization and reduced memory footprint. Each grid-cell may be further partitioned into sub-containers to more efficiently provide space pruning during query operations. According to one approach, structures maintained to track existence of objects in a descendent hierarchy.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: March 26, 2013
    Assignee: Cadence Design Systems, Inc
    Inventors: Mark Hahn, Laurent Volpe, Guruprasad G. Rao
  • Patent number: 8401828
    Abstract: Systems and methods for simulating and verifying an analog mixed signal design provide an analog mixed signal testbench configured to verify analog parameters of the design. The testbench can include a mechanism to fetch a value of an analog object in an analog portion of a mixed signal design. The testbench mechanism can include an argument specifying the name of the object and the analog quantity to be fetched for that object. The testbench can retrieve estimated values and can further specify timing constraints specifying absolute times or events at which values are to be measured and returned.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: March 19, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prabal K. Bhattacharya, Timothy Martin O'Leary, William Scott Cranston, Walter Hartong
  • Patent number: 8402438
    Abstract: Disclosed is a process, system, and computer program product for generating a verification test or verification environment for testing and verifying software or mixed software/hardware. Object code is analyzed to generate and setup test information and environments. The object code is analyzed to identify information about the software important or relevant for the verification process. Based upon the information generated from the object code, one or more verification environments or tests can be generated for testing and verifying the software or mixed hardware/software.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: March 19, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jason Robert Andrews, Markus Winterholer, Ronald Joseph Pluth
  • Patent number: 8402417
    Abstract: Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 19, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventor: Gilles S. C. Lamant
  • Patent number: 8402421
    Abstract: A method and system for subnet defect diagnostics through fault compositing is disclosed. A testing apparatus generates callout data for an integrated circuit device under test. A computer received the callout data, which includes a list of faults. Each fault of the list of faults has associated with it one or more failures and/or conflicts. In order to explain the failures, two or more faults are selected and composited, yielding a composite fault having a composite conflict count. The composite fault is assigned a score based on the composite conflict count, which score determines a candidate composite that best explains the faults of the list of faults. This procedure may be repeated to explain all the failures.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: March 19, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thomas Webster Bartenstein, Joseph Michael Swenton
  • Patent number: 8397194
    Abstract: According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout circuit representation on the schematic circuit representation with highlighting that indicates the LVS errors. The method of such an embodiment compares a layout netlist against a schematic netlist in order to identify the layout-versus-schematic errors, generates a graphical representation of the layout netlist and a graphical representation of the schematic netlist, displays an overlay of the graphical representation of the layout netlist with the graphical representation of the schematic netlist and then, highlights the identified layout-versus-schematic errors that are present.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prasanti Uppaluri, Doug Den Dulk
  • Patent number: 8397113
    Abstract: A method and system for identifying power defects using test pattern switching activity is disclosed. In one embodiment, a plurality of test patterns is applied to a circuit under test, and failure test patterns are identified from the plurality of test patterns by comparing the test result with the predicted test result. A switching activity count is obtained for each of the plurality of test patterns. Based on the switching activity count, ranks for each of the plurality of test patterns are provided. A correlation analysis is performed between the failure test patterns and the ranks of the switching activities. When there is a high correlation between the failure test pattern and the ranks of the switching activities, it is determined that the circuit likely contains a power defect. A power defect analysis is performed under the presence of the high correlation.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: March 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thomas W. Bartenstein, Patrick Wayne Gallagher
  • Patent number: 8392864
    Abstract: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: March 5, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: David White, Eric Nequist
  • Patent number: 8392868
    Abstract: A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle count thresholds for respective power grid regions of the non-uniform power grid; and determining whether respective numbers of toggles by scan elements of the scan chain within one or more respective power grid regions meet respective toggle count thresholds for the one or more respective regions during at least one scan-shift cycle in the course of scan-in of a test pattern to the scan chain.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: March 5, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Senthil Arasu Thirunavukarasu, Shaleen Bhabu, Vivek Chickermane