Patents Assigned to Cadence Design Systems
  • SYSTEM AND METHOD FOR DYNAMICALLY INJECTING ERRORS TO A USER DESIGN
    Publication number: 20120317533
    Abstract: A method and system for dynamically injecting errors to a user design is disclosed. In one embodiment, the user design having internal states and parameters is run in a design verification system. A reconfigurable design monitor monitors a plurality of error conditions based on the internal states and parameters of the user design and generates a trigger event when a predefined error condition is met. The reconfigurable design monitor transmits a trigger event to an error injector. The error injector injects dynamic errors associated with the triggering event to the user design via a control path to test the user design under the predefined error condition.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Applicant: Cadence Design Systems, Inc.
    Inventors: GAVIN ZAWALSKI, Mark Lewis
  • Method and system for verifying electronic designs having software components
    Patent number: 8326592
    Abstract: Disclosed is a method and system for providing an improved and flexible approach for handling models of hardware and software designs for verification activities. The semantics of the software and hardware are mapped to allow correct interfacing between the hardware and software models. This allows designers to more efficiently and accurately perform hardware/software co-verification.
    Type: Grant
    Filed: December 20, 2008
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth L. McMillan
  • System and method for implementing image-based design rules
    Patent number: 8327299
    Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D MDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
  • Template-based real number behavioral modeling
    Patent number: 8327303
    Abstract: A method and system for template-based behavioral model creation for behavioral modeling is disclosed. A design characterization and modeling (DCM) tool has a number of templates for different circuits. A designer chooses a template and customizes the template with a number of parameters and optionally pin assignments. The DCM tool generates a behavioral model that has real wire (“Wreal”) capability. The transistor level design is simulated with a testbench according to the parameters to generate Wreal calibration information. The behavioral model uses the Wreal calibration information in behavioral modeling to provide quick behavioral processing of the behavioral model with the benefit of increased accuracy provided by the Wreal calibration information, for example. Optionally, the DCM tool generates another testbench that validates the analog and behavioral models.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Paul C. Foster, Walter E. Hartong, T. Martin O'Leary
  • System and method for process rules editors
    Patent number: 8327315
    Abstract: According to various embodiments of the invention, a system and method for editing process rules for circuit design through a graphical editor is provided. In some embodiments, the graphical editor is a circuit design tool that provides the user of the tool, such as a circuit designer or process engineer, the ability to visualize, modify, create, or remove process rules through a graphical user interface (“GUI”). These process rules, also known as constraints or circuit design constraints, relate to the layout of circuits and is grouped into constraint groups (also known as “circuit design constraint groups”) that can be associated to specific circuit design objects.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sandipan Ghosh, Hitesh Marwah, Pawan Fangaria, Arbind Kumar
  • Amplitude modulation-phase modulation decomposition method for phase noise simulation of oscillators with large time-constant
    Patent number: 8326593
    Abstract: Embodiments may include methods, systems, and computer-readable storage mediums that may be used to simulate phase noise for an oscillator circuit. In some embodiments, a method of simulating phase noise for an oscillator circuit may include providing an oscillator circuit description. A time-domain representation of a small signal phase noise of the oscillator circuit description may be determined. A shooting Newton matrix representation of the time-domain representation of the small signal phase noise may be generated. The shooting Newton matrix representation may be augmented to include a phase-shift factor and a pinning equation. The augmented shooting Newton matrix representation may be solved to determine a signal output of the oscillator circuit.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yu Zhu, Xiaolue Lai
  • Method and system for implementing a waveform viewer
    Patent number: 8325188
    Abstract: Systems and methods for storing waveform data and outputting data to a waveform viewer are disclosed. A waveform is segmented into a plurality of segments, and data describing each segment is stored at several levels of resolution. When a user wishes to view a portion of the waveform, the appropriate segments of the waveform are identified, and the appropriate levels of resolution are selected. The data describing the appropriate segments at the appropriate levels of resolution are output to a waveform viewer. An index may be provided to aid in selection of the appropriate data. Various methods for compression of the data are also supported.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joel R. Phillips, Sherry Solden, Henry C. Chang, Kenneth S. Kundert, Ted Vucurevich
  • Integrated DMA processor and PCI express switch for a hardware-based functional verification system
    Patent number: 8327039
    Abstract: A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ching-Ping Chou, Su-Jen Hwang, Teng-I Yu
  • Place and route tool that incorporates a metal-fill mechanism
    Patent number: 8327300
    Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thanh Vuong, William H. Kao, David C. Noice
  • Synchronized envelope and transient simulation of circuits
    Patent number: 8326591
    Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qian Cai, Dan Feng, Bruce W. McGaughy, Jun Kong, Rendong Lin
  • Method and mechanism for modeling interconnect structures for integrated circuits
    Patent number: 8316336
    Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: David Overhauser
  • Method and system for optimally placing and assigning interfaces in a cross-fabric design environment
    Patent number: 8316337
    Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharya, Vikas Kohli, Tarun Beri, Rahul Verma
  • Method and mechanism for implementing extraction for an integrated circuit design
    Patent number: 8316331
    Abstract: An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eric Nequist, Richard Brashears, Matthew A. Liberty, Michael C. McSherry
  • Constraint minimization method for formal verification
    Patent number: 8316332
    Abstract: The present disclosure relates to a method for minimizing constraints in the formal verification of an integrated circuit design. The method may include obtaining an unisolated list of constraints initially comprising all known constraints for the integrated circuit design and obtaining an isolated list of constraints initially comprising none of the known constraints. The method may further include attempting to prove an assertion without the known constraints and determining if the assertion is valid. The method may further include updating the isolated list of constraints.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pradeep Goyal, Alok Jain
  • Reticle and technique for multiple and single patterning
    Patent number: 8316329
    Abstract: Double patterning is achieved with a single reticle while maintaining the integrity of in-scribe patterns and without blading the reticle. In-scribe structures may or may not be double patterning. For example, elements such as electrical test structures might have features that are so closely spaced that double pattering is desired. However, elements such as optical alignment marks might not require double patterning. For those elements for which double patterning is not desired, a first sub-array of the reticle has a pattern for the element, whereas the corresponding location in a second sub-array has a blank. By the corresponding location, it is meant the location on the reticle that would be exposed to the same target region to which the element would be exposed if the reticle were used for double patterning. Thus, the blank prevents target region from being exposed more than once.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Rodney Rigby, James Frisby, Aaron Parr, Yasuhisa Yamamoto
  • System and method for applying phase effects of mask diffraction patterns
    Patent number: 8316326
    Abstract: In accordance with some embodiments, a method is provided for creating a photolithographic component, comprising: determining a target pattern for a circuit layout, the target pattern comprising target features; identifying a set of periodic target features within the target pattern; calculating a relationship between feature and pitch for the set of periodic target features; and determining a mask pattern from the target pattern using the relationship, wherein the mask pattern has a set of periodic mask features configured to result in projection of a first subset of the set of periodic target features when exposed to a light source that induces a first phase effect, and configured to result in projection of a second subset of the set of periodic target features when exposed to a light source that induces a second phase effect. In further embodiments, the method outputs the mask pattern as a mask dataset.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Christophe Pierrat
  • Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout
    Patent number: 8316342
    Abstract: A method of interconnecting a first plurality of electronic components and a second plurality of electronic components to form an electronic circuit includes exporting a first netlist representing a first interconnection of the first electronic components in a first design entry tool, exporting a second netlist representing a second interconnection of the second electronic components in a second design entry tool, providing at least a first interface from the second plurality to the first plurality in the second design entry tool, populating the first interface through the first design entry tool, and exporting a third netlist representing the first interface from the second plurality to the first plurality from the second design entry tool, wherein the third netlist stitches the first netlist to the second netlist.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: November 20, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Taranjit Kukal, Chris Cheung, Vikas Kohli, Keith Felton, Frank X. Farmar, Steven R. Durrill
  • Systems and methods for lithography-aware floorplanning
    Patent number: 8312398
    Abstract: The present invention is directed towards designing integrated circuit and provides systems and methods for lithography-aware floorplanning. According to one embodiment of the invention, a method for circuit floorplanning is provided. The method comprises generating a floorplan through a floorplanner, performing a lithography-analysis within the floorplanner on at least a portion of the floorplan, and generating one or more violations that result from the lithography-analysis. Some embodiment, in addition to viewing a floorplan, further comprise of modifying the floorplan. Furthermore, some embodiments provide a method that further comprises fixing the violations that result from the lithography analysis.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: November 13, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chayan Majumder, Pawan Fangaria
  • Method and system performing RC extraction
    Patent number: 8312406
    Abstract: A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 13, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Li J. Song, Taber Smith, Hao Jl, Zhan-Zhong Yao
  • Method and apparatus for broadband electromagnetic modeling of three-dimensional interconnects embedded in multilayered substrates
    Patent number: 8312402
    Abstract: Systems and methods for modeling a multilayer integrated circuit include three-dimensional interconnect models in multilayered substrates for greater accuracy. Mesh models are used to resolve effects of nearby elements and grid models are used to resolve effects of far-away elements. Sidewall mesh elements of three-dimensional interconnects are projected onto parallel (or substantially parallel) grids between the top and bottom walls of the interconnects so that grid models can be used to resolve three-dimensional effects of interconnects in multilayered substrates.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: November 13, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Vladimir Okhmatovski, Mengtao Yuan, Rodney Phelps