Abstract: The present disclosure relates to a method, apparatus, and system for locking a phase locked loop (PLL). The method may include receiving a reference signal at a phase locked loop (PLL) circuitry having a first PLL circuitry and a second PLL circuitry. The first PLL circuitry may include a fixed frequency oscillator. The method may further include adjusting a division ratio using, at least in part, a fractional divider circuitry in communication with the fixed frequency oscillator, to generate a feedback signal having a substantially equal frequency and a substantially equal phase in relation to a reference frequency. The method may also include receiving the feedback signal and the reference frequency at a phase detector.

Abstract: The present disclosure relates to a computer-implemented method for assigning pins in an electronic design. The method may include generating a pin list associated with the electronic design, the pin list having a one or more pins that are directly and indirectly connected with at least one of a master partition and a clone partition. The method may further include sorting one or more pins within the pin list based upon, at least in part, a number of local connections to generate a sorted pin list and selecting a first pin having a highest number of local connections of the sorted pin list as a reference pin. The method may also include selecting a partition of the reference pin, as a reference partition and identifying one or more alignment zones for every connected pair of pins in the sorted pin list. The method may further include transforming all alignment zones to the reference partition using a depth-first-search.

Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.

Abstract: In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically produce the physical layout wire-load model and to calculate net length and delay for each optimization iteration.

Abstract: An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement.

Abstract: Disclosed is an improved method and system for implementing and analyzing power switch configurations. Described is a novel approach to minimize the number of power switches required for a power domain and to automatically find the locations of those power switches subject to the constraints of saturation current and maximum IR-drop on the power switches. This approach uses a fast static power consumption analysis tool to compute the current and IR drop through the power switches. The approach can apply to both column and ring style power switch insertion methodologies.

Abstract: A method and system are provided for adaptively modeling and simulating high speed response of a transmission line. A simulation unit maintains a plurality of curve approximation options for modeling the transmission line. The suitability of a predefined primary one of the curve approximation options for modeling is determined based on frequency-domain modal scattering parameters obtained according to frequency-dependent data characterizing the transmission line. One of the options is selectively executed in response to the determination, in order to generate a macromodel of the transmission line. The primary option is executed upon determination of suitability, while a secondary one of the curve approximation options is alternatively executed upon determination of non-suitability. Transient simulation is then executed upon the resulting macromodel of the transmission line.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

Abstract: A system, method, and software program for facilitating the assignment of cell specifications to a plurality of cells of a system design. The methods include generating a plurality of candidate cell specifications that meet the specification for the system design. In one embodiment, the method entails using information related to intra-range preference for cell specifications to generate a set of alternative system pareto-optimal solutions which define a boundary of a region of candidate cell specifications. In another embodiment, the method entails generating a substantially uniform set of candidate cell specifications using a prediction-based performance model, such as support vector regression model or cluster-weighted model, an optimizing algorithm such as conjugate-gradient or Markov Chain Monte Carlo Method, and a sample density model.

Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Abstract: In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.

Abstract: A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography using colored space tiles. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design. Colored space tiles may be utilized to perform the detail routing.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.