Patents Assigned to Cadence Design Systems
  • Publication number: 20100324878
    Abstract: Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.
    Type: Application
    Filed: June 23, 2009
    Publication date: December 23, 2010
    Applicant: Cadence Design Systems, Inc.
    Inventors: Brian LEE, Srinivas DODDI, Ron PYKE, Taber SMITH, Emmanuel DREGE
  • Publication number: 20100321055
    Abstract: Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.
    Type: Application
    Filed: August 31, 2010
    Publication date: December 23, 2010
    Applicant: Cadence Design Systems, Inc.
    Inventors: Joseph Swenton, Thomas Bartenstein, Richard Schoonover, David Sliwinski
  • Patent number: 7856613
    Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: December 21, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Milind Weling, Judy Huckabay, Abdurrahman Sezginer
  • Patent number: 7853905
    Abstract: The present invention relates to performing early design for testing (DFT)-aware prototyping of a design. Unlike prior approaches, the improvement analyzes and considers the impact of test structures at a very early stage of the design process. This allows test structures to be considered and addressed in a more efficient iterative and incremental way, which reduces design cycle time and reduces costs.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kit Lam Cheong, Ping-Chih Wu, Weibin Ding, Louis Liu, Yiqun Ding
  • Patent number: 7853910
    Abstract: Method, system, and computer program product for analyzing circuit structures for parasitic effects are provided. Data from a previous parasitic effect analysis of a circuit structure is used to perform parasitic effect analysis on another circuit structure even when the circuit structures are not identical, provided the circuit structures are similar.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhenhai Zhu, Joel Phillips, Zuo-Chang Ye
  • Patent number: 7853903
    Abstract: An improved method and mechanism for verification of an electrical circuit design is provided. The method and system simultaneously provides the coverage advantage of formal verification with the scaling efficiencies of simulation. In one approach, the method and system generates an intelligent set of test vectors off a resolution proof. The intelligent set of test vectors can be used to simulate the circuit design for complete coverage without having to test the entire set of possible variable assignments for the CNF formula corresponding to the circuit design.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Evgueni Goldberg, Felice Balarin
  • Patent number: 7853904
    Abstract: Disclosed is an approach for modeling and correcting for the effects of reflections during lithography processing. Thickness differences across the surfaces in different integrated circuit layers may result in reflectance-related variations. The variations may be modeled and accounted for during the design process for the integrated circuit.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: December 14, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: David White
  • Patent number: 7849423
    Abstract: A photomask dataset corresponding to a target-pattern is verified by simulating a resist-pattern that will be formed in a resist layer by a lithography process, simulating an etched-pattern that will be etched in a layer by a plasma process wherein said simulation comprises calculating a flux of particles impacting a feature, and determining whether the etched-pattern substantially conforms to the target-pattern.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: December 7, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Bayram Yenikaya, Devendra Joshi, Paul A. Fornari, Jesus O. Carrero, Abdurrahman Sezginer
  • Patent number: 7844438
    Abstract: A method to analyze and correct dynamic power grid variations in an IC includes performing a dynamic power grid analysis of the circuit, identifying an excessive dynamic power grid voltage fluctuation from the analysis, and modifying the circuit to reduce the excessive dynamic power grid fluctuation.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: November 30, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nishath Verghese, Kenneth Tseng
  • Patent number: 7836419
    Abstract: Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Cadence Design Systems, Inc
    Inventors: Bruce W. McGaughy, Jun Kong
  • Patent number: 7835890
    Abstract: The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: November 16, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Lifeng Wu, Zhihong Liu, Alvin I. Chen, Jeong Y. Choi, Bruce W. McGaughy
  • Patent number: 7836102
    Abstract: A method and system for enhancing software documentation and help systems. In one embodiment, a virtual library for a selected combination of tools is created. The virtual library is then linked to the tools in the selected combination of tools. In another embodiment, a combination of tools for designing a complex software system is selected from one or more software releases. The one or more software releases comprises a plurality of available tools. The selected combination of tools comprises less than all of the plurality of available tools. Each of the plurality of available tools is associated with one or more documents. Access to only those one or more documents associated with tools in the selected combination of tools is provided.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: November 16, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: Gurbir Singh
  • Patent number: 7831942
    Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: November 9, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
  • Patent number: 7827519
    Abstract: Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: November 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis K. Scheffer, David White
  • Patent number: 7827023
    Abstract: A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: November 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: William F. Beausoleil, Beshara G. Elmufdi, Mitchell G. Poplack, Tai Su
  • Patent number: 7824828
    Abstract: A method and system for dose correction of a particle beam writer is disclosed. The method and system includes reading a file of writing objects that includes dose intensity, calculating a rate of dose intensity change between adjacent writing objects, selecting a writing object that may need accuracy improvement of dose correction based on the rate of dose intensity change, and improving accuracy of the dose correction of the writing object that is selected and its adjacent objects.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: November 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Akira Fujimura, Daisuke Hara, Katsuo Komuro, Takashi Mitsuhashi
  • Patent number: 7827017
    Abstract: A system and method for performing circuit simulation is described. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked. Mechanisms are provided that allow for viewing, measurement or other manipulation of signals at specific locations in a circuit design for simulation, such as parameters that include observation points which are implemented using probes. One approach to executing a measurement is via a controllable and flexible control statement, which in one embodiment is the “run” statement. Improved interfaces for viewing, controlling, and manipulating simulations and simulation results are also provided.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: November 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Patent number: 7823095
    Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: October 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eitan Cadouri, Krzysztof A. Kozminski, Haifang Liao, Kenneth Mednick, Roland Ruehl, Mark A. Snowden
  • Patent number: 7823104
    Abstract: Some aspects provide determination of a function to rectify functional differences between netlist G1 and netlist G2 having inputs V. The determination may include determination of a signal s of netlist G1 that can be re-synthesized so as to correct the functional differences between netlist G1 and netlist G2, assignment of respective static values to a first plurality of inputs V, assignment of respective initial values to a second plurality of inputs V, determination of a first function based on the assigned static values, the assigned initial values, a first error function reflecting the difference between outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 0, and a second error function reflecting the difference between the outputs of netlist G1 and netlist G2 for each vector of inputs V in a case that s equals 1.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: October 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Cheng-Ta Hsieh, Yifeng Wang, Yung-Te Lai, Chih-Chang Lin
  • Patent number: 7821276
    Abstract: Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeating and/or predictable sequence of care bits (a care bit pattern) that can be used by a tester to cause the exercise of the area and collect emissions caused by exercising the area. Such emissions can be used for analysis and debugging of the circuit and/or a portion of it. Aspects can include providing a synchronization signal that can be used by a tester to allow sensor activation at appropriate times.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: October 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joseph Swenton, Thomas Bartenstein, Richard Schoonover, David Sliwinski