Abstract: In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing.

Abstract: A system and method for improved electron beam writing that is capable of taking design intent, equipment capability and design requirements into consideration. The system and method determines an optimal writing pattern based, at least in part, on the received information.

Abstract: An adaptive mesh of virtual nodes is provided to analyze the performance of a power/ground plane pair having an irregular shape. Plane transmission line characteristics and regional modal resonances can be modeled accurately, and with a significant decrease in simulation time as compared to traditional methods. A variable-sized cell structure is constructed with smaller cells in irregular regions and with larger cells in uniform regions. Grid nodes may thus stay aligned along length and width to allow parameters of equivalent circuit models to be scaled appropriate to the cell size.

Abstract: Disclosed are methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments disclosed herein provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments disclosed herein are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.

Abstract: Methods and systems for correcting inter-level variations are disclosed. One approach addresses thickness and/or topological variations based upon layers in an IC design that do not allow the placement of dummy fill, in which dummy fill is added to certain layers of the IC to reduce process variations caused by other layers in the semiconductor devices. To accomplish this, layers in the design that cannot accommodate dummy fill are modeled to determine their topological variations. Other layers that are capable of receiving dummy fill are then analyzed to receive the correct quantity and distribution of dummy fill to correct for the topological variations from the non-dummy fill layers.

Abstract: A pertubative approach based on the Born approximation resolves weakly nonlinear circuit models without requiring explicit high-order device derivatives. Convergence properties and the relation to Volterra series are discussed. According to the disclosed methods, second and third order intermodulation products (IM2, IM3) and intercept points (IP2, IP3) can be calculated by second and third order Born approximations under weakly nonlinear conditions. A diagrammatic representation of nonlinear interactions is presented. Using this diagrammatic technique, both Volterra series and Born approximations can be constructed in a systematic way. The method is generalized to calculate other high-order nonlinear effects such as IMn (nth order intermodulation product) and IPn (nth order intermodulation intercept point). In general, the equations are developed in harmonic form and can be implemented in both time and frequency domains for analog and RF circuits.

Abstract: A multiple-input follower amplifier is coupled through a configuration of switching devices to an upper reference voltage at a number of its inputs and to a lower reference voltage at the remaining number of its inputs to form a voltage interpolator. The output of the voltage interpolator is a voltage between the upper and lower reference voltages proportional to the number of inputs coupled to each reference voltage. The voltage interpolator may be constructed so that the interpolated voltage may be selected through a reduced number of signal lines, such as by a row/column selection scheme. A voltage reference circuit providing the upper and lower reference voltages may also implement a row/column selection mechanism, thereby allowing a decoding scheme common to both a voltage reference circuit and a voltage interpolator in a digital-to-analog converter.

Abstract: A method for migrating a netlist from one set of library cells to a new set of library cells with minimal time and effort and without loss of information within an ASCI environment. This methodology ensures that during translation logic equivalence and scan configurations are maintained in the new technology libraries. Additionally, a complete migration of the constraints from the original netlist to the new netlist is also performed. Designer engineers no longer have to start from RTL and execute a complete resynthesis to translate an original design from one technology library to a new technology library.

Abstract: A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining a testbench for simulating the IC and a verification plan for evaluating simulation results; using the testbench to simulate variations in power levels of the power domains of the IC; and using the verification plan to evaluate the simulation results for the power domains of the IC.

Abstract: Method and system for crosstalk analysis relating to a statistical crosstalk path delay model that fits into existing static timing framework with little overhead in performance and capacity. More realistic models or assumptions are utilized rather than the more aggressive and less likely deterministic model.

Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Abstract: A graphical specification entry interface allows a circuit designer to define relative placement of repeating circuit component cells. The repetitive placement specifications are used to generate a repetitively structured circuit cell which may be subsequently installed into a physical circuit medium. The system simplifies user interaction in generating repetitive circuit structures such as semiconductor memory and, while affording heretofore unavailable topological diversity of such circuits.

Abstract: In one embodiment of the invention, a method of simulating a circuit is disclosed including simulating an analog component of the circuit over a first simulation time period with a first envelope simulation; adaptively switching from simulating the analog component with the first envelope simulation to simulating the analog component with a transient simulation over a second simulation time period; and adaptively switching from simulating the analog component with the transient simulation to simulating the analog component with a second envelope simulation over a third simulation time period. The adaptive switching from the first envelope simulation to the transient simulation may be in response to the envelope simulation accuracy falling below a predetermined level of accuracy in comparison with a transient simulation or in response to the second simulation time period including expected digital transitions where one or more digital events may occur to change the analog input signals to the analog component.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.

Abstract: Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.

Abstract: Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving element; and creating in the computer readable medium clock gate logic that suspends saving of new states by the single state saving element upon the occurrence of a first state retention signal in preparation for power shut off.

Abstract: A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.

Abstract: An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.

Abstract: In one embodiment of the invention, a method of scan testing an integrated circuit is disclosed. The method includes scanning a first test vector and a second test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch, a scan latch, and a functional latch; and applying the first and the second test vectors sequentially in a delay fault test via the plurality of scan registers to a combinational logic circuit coupled to the plurality of scan registers.