Abstract: Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern.

Abstract: Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Abstract: A hardware emulator having a variable input emulation group is described. Each emulation group comprises two or more processors, where one of the processors (a first processor) is coupled to a data input selector and another one of the processors (a second processor) processes a first amount of data received from a data array. The data input selector receives the first amount of data and a second amount of data from the data array, and selects a third amount of data from among the first and second amounts of data. The third amount of data is provided to the first processor for evaluation.

Abstract: A method of particle beam lithography includes selecting at least two cell patterns from a stencil, correcting proximity effect by dose control and by pattern modification for the at least two cell patterns, and writing the at least cell two patterns by one shot of the particle beam after proximity effect correction (PEC).

Abstract: A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.

Abstract: A method, system, and computer program product are disclosed for generating a pattern signature to represent a pattern in an integrated circuit design. In one approach, the method, system and computer program product transform pattern data, two dimensional data for the pattern, into a set of one dimensional mathematical functions, compress the set of one dimensional mathematical functions into a single variable function, compress the single variable function by calculating a set of values for the single variable function, and generate a pattern signature for the pattern from the set of values.

Abstract: Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer are provided. A semiconductor structure can include first, second and third layers. The first conducting layer may be etched to form a first trench for the first conductive trace. A layer of material on the second layer in the first trench can define a patch area, wherein the patch area is disposed in a location where the first trench crosses over the third electrical trace. A second trench may be etched in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench, leaving material of the layer under the patch area.

Abstract: A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.

Abstract: A method for particle beam lithography, such as electron beam (EB) lithography, includes forming a plurality of cell patterns on a stencil mask and shaping one or more of the cell patterns with a polygonal-shaped contour. A first polygonal-shaped cell pattern is exposed to a particle beam so as to project the first polygonal-shaped cell pattern on a substrate. A second polygonal-shaped cell pattern, having a contour that mates with the contour of the first polygonal-shaped cell pattern, is exposed to the particle beam, such as an electron beam, so as to project the second polygonal-shaped cell pattern adjacent to the first polygonal-shaped cell pattern to thereby form a combined cell with the contour of the first polygonal-shaped cell pattern mated to the contour of the second polygonal-shaped cell pattern. The polygonal-shaped contour of the first and second cell patterns may comprise a rectilinear-shaped contour.

Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.

Abstract: Disclosed are a method, a system, and a computer program products for implementing model exchange in a system design. In various embodiments, the method or system receives a model exchange request from a client where model exchange request comprises a first synchronization record which comprises a delta of both a program aspect and a data aspect between a system design on the client and a system design on the server, implements the first model exchange request by processing the first model exchange, generates a second synchronization record in response to the first model exchange, transmitting the second synchronization record to the first client by using a fusion technology, and displaying a result of implementing the first model exchange request or storing the result in a tangible computer readable medium.

Abstract: A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.

Abstract: Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.

Abstract: State retention cells of a test circuit embedded in an electrical circuit are interconnected to form one or more scan chains. The scan chains are interconnected so that unknown states, or X-states, are shifted through the scan chains in an order other than the order in which the states were captured by the state retention cells of the scan chain. Such reordering of response states in individual scan chains may be used to align the X-states across multiple scan chains to achieve higher test compression scan register circuit testing.

Abstract: An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in a design. Basically, the configurable design is an all-inclusive design having a large set of features, including varying interfaces, FIFO depths, and other features. Then, a derived design is generated by removing configurable constructs from the configurable design based on a specification, typically a customer specification received from a customer for a particular design. The specification indicates which configurable constructs are to be included in a derived design. Thereafter, the derived design is synthesizable in logic.

Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.

Abstract: The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules analysis can be used to identify specific areas of a layout that can then be analyzed in detail using models. This approach provides numerous advantages. It allows the models-based analysis tool to concentrate upon portions of the layout that requires greater attention and allocate fewer resources towards the areas less critical to the yield.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: Double patterning is achieved with a single reticle while maintaining the integrity of in-scribe patterns and without blading the reticle. In-scribe structures may or may not be double patterning. For example, elements such as electrical test structures might have features that are so closely spaced that double pattering is desired. However, elements such as optical alignment marks might not require double patterning. For those elements for which double patterning is not desired, a first sub-array of the reticle has a pattern for the element, whereas the corresponding location in a second sub-array has a blank. By the corresponding location, it is meant the location on the reticle that would be exposed to the same target region to which the element would be exposed if the reticle were used for double patterning. Thus, the blank prevents target region from being exposed more than once.

Abstract: A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-circuit layout based on such characterizations.