Patents Assigned to Cadence Design Systems
  • Patent number: 7627463
    Abstract: A system, method, computer program and article of manufacture for channel analysis. Channel analysis is a multi gigahertz capacity time domain circuit simulation which uses the impulse response of the channel to determine optimum filter settings and to produce wave form plots in a fraction of the time of circuit simulation.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: December 1, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kumar Chidhambarakrishnan
  • Patent number: 7627072
    Abstract: A frequency-to-current converter includes a digitally selectable capacitor, a sampling capacitor, an integrator circuit and an output transconductor. The sampling capacitor is operatively coupled via a first switch to the digitally selectable capacitor. The first switch is operated by a first clock pulse from a clock generator responsive to a reference clock. The integrator circuit has an output operatively coupled via a second switch to the sampling capacitor. The integrator circuit has an output operatively coupled to a control terminal of the transistor. The second switch is operated by a second, non-overlapping clock pulse from the clock generator. A current output by the frequency-to-current converter in response to the continuous question of first and second switches is linearly proportional to the frequency of the reference clock and the capacitance of the digitally selectable capacitor.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: December 1, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eric Naviasky, Michelle Williams
  • Patent number: 7627842
    Abstract: Disclosed are techniques for performing the verification of circuits where corresponding signals in the circuits or specifications are encoded differently and/or redundancy occurs in the signals. Verification, such as logic equivalence checking of circuits, can be performed where the corresponding signals in the two circuits are encoded differently, and/or redundancy occurs in the signals.
    Type: Grant
    Filed: June 1, 2004
    Date of Patent: December 1, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kei-Yong Khoo, Chih-Chang Lin
  • Patent number: 7627847
    Abstract: A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: December 1, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Louis K. Scheffer
  • Patent number: 7624364
    Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: November 24, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
  • Patent number: 7624367
    Abstract: Disclosed is a method, system, and computer program product for routing, modeling routes, and measuring congestion. In some embodiments, Gcells are implemented with reduced number of nodes to facilitate route modeling and congestion measurement. Some embodiments are particularly suitable for direct congestion and routing analysis of diagonal routing paths. In this way, congestion analysis can be directly performed along diagonal boundaries for diagonal routes, without requiring association with Gcell boundaries on Manhattan routing layers.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: November 24, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan Frankle, John H. Gilchrist, III, Anish Malhotra
  • Patent number: 7620918
    Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: November 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Yung-Te Lai, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin
  • Patent number: 7620922
    Abstract: An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a plurality of corresponding constraint instances. Each constraint instance variably indicates an effective constraining limit and degree of consumption for at least one of the parametric resources. At least one of the constraints is selectively adjusted by a predetermined over-constraining amount, and the circuit routing solution is preliminarily modified by applying at least one routing action selected responsive to the constraint adjustment. The potential impact upon constraint compliance is evaluated, including generating a relative cost measure for the preliminary modification of the circuit routing solution, based at least partially upon each of the constraint instances.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: November 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Richard Woodward, Randall Lawson, Greg Horlick
  • Patent number: 7620919
    Abstract: Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: November 17, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Yung-Te Lai, Bret Siarowski, Kei-Yong Khoo, Chih-Chang Lin
  • Patent number: 7617084
    Abstract: Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and mechanism for resolving the issue of simultaneous debugging of hardware represented by an HDL, e.g., Verilog or VHDL, and software, e.g., represented by C, C++, SystemC code. This approach overcomes the problem of the HDL portion of the design being inaccessible when C, C++ or SystemC code is debugged.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: November 10, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Douglas J. Koslow, Leonardo Valencia, Mark Harris
  • Patent number: 7617465
    Abstract: Disclosed is a system and method for performing latchup checks for an IC design. In one approach, partitioning is used to create separate sections of the geometry to analyze. The data is then checked by performing graph manipulations.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: November 10, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Eitan Cadouri
  • Patent number: 7613969
    Abstract: A method and system for clock skew independent scan chains. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan register of the plurality is associated with a first clock network, and a second mux-D scan register of the plurality is associated with a second clock network. The plurality of mux-D scan registers have a scan mode. The first mux-D scan register and the second mux-D scan register become clock skew independent by controlling a scan-enable signal and a clock signal.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: November 3, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sandeep Bhatia
  • Patent number: 7614028
    Abstract: Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: November 3, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eric Nequist, Richard Brashears
  • Publication number: 20090271167
    Abstract: A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.
    Type: Application
    Filed: December 30, 2008
    Publication date: October 29, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Bing ZHU, Tsair-Chin Lin, Tung-sun Tung, Jingbo Gao
  • Patent number: 7610570
    Abstract: An improved method and mechanism for designing and verifying an electrical circuit design is provided using an improved SAT-solver which uses complete assignments and systematic local search to provides improved performance. In one approach, the sat-solver maintains a complete assignment that is changed one variable at a time. A variable is fixed within the falsified set of clauses.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 27, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Evgueni Goldberg
  • Patent number: 7610571
    Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: October 27, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Yonghao Chen
  • Patent number: 7606693
    Abstract: A solution of a first set of equations of the time-varying electrical response of a circuit is determined between pairs of adjacent time points ti and ti+1 based on predicted electrical responses of the devices at time point ti+1 and as a function of the initial temperatures of the circuit devices at time point ti. A solution of a second set of equations of the time-varying temperature responses of devices of the circuit is determined (1) after each iteration of the first set of equations and as a function thereof or (2) at each time point ti+1 and as a function of the solution of the first set of equations at the time point to determine the corresponding temperature response of the circuit. The solutions of the first and second sets of equations at one or more of the points in time are displayed.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: October 20, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Min-Che Jeng, Yutao Ma, Zhihong Liu
  • Patent number: 7606698
    Abstract: A method and apparatus for sharing data between processors within first and second discrete clusters of processors. The method comprises supplying a first amount of data from a first data array in a first discrete cluster of processors to selector logic. A second amount of data from a second data array in a second discrete cluster of processors is also supplied to the selector logic. The first or second amount of data is then selected using the selector logic, and supplied to a shared input port on a processor in the first discrete cluster of processors. The apparatus comprises selector logic for selecting between input data supplied by a first data array and a second data array. The data arrays are located within different discrete clusters of processors. The selected data is then supplied to a shared input port on a processor.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: October 20, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Beshara G. Elmufdi, Mitchell G. Poplack
  • Patent number: 7603642
    Abstract: The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: October 13, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pero Subasic, Xuejin Wang, Enis A. Dengi, Ibraz H. Mohammed
  • Patent number: 7603643
    Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: October 13, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Thaddeus Clay McCracken, Jong-Chang Lee, Ping-Chih Wu, Cecile Nghiem, Kit Lam Cheong, Patrick John Eichenseer