Patents Assigned to Cadence Design Systems
  • Patent number: 7579886
    Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: August 25, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael M. Hufford, Eric Naviasky, Tony Caviglia
  • Patent number: 7574685
    Abstract: An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: August 11, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaopeng Dong, Inhwan Seo, William Kao, David C. Noice, Gary Nunn
  • Patent number: 7574342
    Abstract: A method is provided for compiling a model for use in a simulation, the method comprising receiving a description of the model; and automatically converting the description into an implementation of the model that is customized for a selected analysis during simulation.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: August 11, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Kenneth S. Kundert
  • Patent number: 7574686
    Abstract: Disclosed is a method, system, and computer program product for implementing a costed-search approach that supports concurrent operation on a multi-CPU system that enables out-of-order search evaluation that does not affect the final outcome of the algorithm. The algorithm is guaranteed to produce identical results when run as a single-threaded application on a single-CPU system. This allows a single regression test suite to be used to test single-threaded and multi-threaded versions of the product.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: August 11, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Randall Lawson, Charles W. Grant
  • Patent number: 7571408
    Abstract: An IC device and layout having one or more layers having route segments and at least some shield segments that are diagonal in orientation. Shield termination segments enclosing a route segment may be diagonal in orientation. Some embodiments describe a method for providing diagonal shielding for a routed net of an IC layout. A route “bloating” method is used where shield position lines (used to position the shielding) are generated by expanding out the dimensions of routes using a bloating shape. The bloating shape that may be dependent on the preferred wiring direction of the layer on which the shielding is provided. After bloating a route, a resulting bloating geometry is identified comprising the area overlapped during the expanding out of the route. The perimeter of the bloating geometry is identified comprising the shield position lines.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: August 4, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Judd M Ylinen, Alexander Khainson
  • Patent number: 7568174
    Abstract: A technique for determining, without having to perform optical proximity correction, when the result of optical proximity correction will fail to meet the design requirements for printability. A disclosed embodiment has application to a process for producing a photomask for use in the printing of a pattern on a wafer by exposure with optical radiation to optically image the photomask on the wafer. A method is set forth for checking the printability of a target layout proposed for defining the photomask, including the following steps: deriving a system of inequalities that expresses a set of design requirements with respect to the target layout; and checking the printability of the target layout by determining whether the system of inequalities is feasible.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: July 28, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Abdurrahman Sezginer, Bayram Yenikaya
  • Patent number: 7567891
    Abstract: The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: July 28, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Zhihong Liu, Lifeng Wu, Jeong Y. Choi, Ping Chen, Alvin I. Chen, Gang Zhang
  • Patent number: 7568177
    Abstract: Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is utilized to control a power signal transfer to at least a portion of the IC.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 28, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Tobing Soebroto, Ankur Gupta, Hendy Kosasih, Richard Chou
  • Patent number: 7562323
    Abstract: A method, system and computer program product for determining aggressor-induced crosstalk in a victim net of a stage of an integrated circuit design is provided. The methodology can include combining a plurality of aggressor nets to construct a virtual aggressor net, determining a current waveform induced on the victim net by the plurality of small aggressor nets, and modeling a current waveform induced by the virtual aggressor on the victim net based on the contribution of the current waveforms determined for the plurality of small aggressor nets. In a further embodiment, the methodology can also comprise evaluating an effect of an aggressor net on a victim net; and including that aggressor net in the virtual aggressor net if its effect is below a predetermined threshold. The effect evaluated by the methodology can, for example, be the height of a glitch induced on the victim net by a transition in the aggressor net.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: July 14, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Xiaoliang Bai, Igor Keller
  • Patent number: 7562330
    Abstract: Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds paths in the layout to satisfy the local constraints and ignores the global constraints. The local constraints are updated before each routing pass to ensure that routes are completed on individual direct connections while also satisfying the global constraint.
    Type: Grant
    Filed: November 6, 2006
    Date of Patent: July 14, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ken Wadland, Sean Bergan, Randall Lawson, Keith Woodword, Richard Woodward
  • Patent number: 7559040
    Abstract: In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in one or more combinational logic paths in the circuit design following the iteration. A clock latency scheduling process is performed that respectively distributes the remaining slack of one or more respective combinational logic paths in the circuit design across respective registers in the circuit design. Another iteration of the logic optimization process is performed that uses at least a portion of the distributed slack to further optimize the circuit design.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: July 7, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Christoph Albrecht, Andreas Kuehlmann, David Seibert, Sascha Richter
  • Publication number: 20090172625
    Abstract: A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 2, 2009
    Applicant: Cadence Design systems, Inc.
    Inventor: Eric Nequist
  • Patent number: 7555736
    Abstract: Disclosed is a method, system, and computer program product for processing design objects, such as vias, for an integrated circuit design. In one approach, pattern matching is employed to perform DRC/LVS for scattering bars and Vias. A library of via combinations can be used to insert scattering bars into design. This approach of using a library can be applied to other structures in design in addition to vias.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: June 30, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Eitan Cadouri
  • Patent number: 7555739
    Abstract: A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method comprises tracking relationships between equivalent figures of the plurality of layout clones, wherein the plurality of layout clones are associated with one another within an equivalence group and propagating an edit made in one of the layout clones within an equivalence group to the other layout clones within the equivalence group.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: June 30, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Arnold Ginetti, Jean-Marc Bourguet, Gerard Tarroux, Laurent Chouraki, Fabrice Morlat, Carole Perrot
  • Patent number: 7551777
    Abstract: Displaying a large data signal includes processing the input data to generate sets of hierarchical multi-resolution histograms that capture the frequency distribution of the signal, in a single pass. Further, the generation of the sets of hierarchical multi-resolution histograms occurs irrespective of an ordinate range of the signal. Further included is generating display vectors, wherein the sets of hierarchical multi-resolution histograms are used to derive the display vectors when a pre-defined criterion is satisfied.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: June 23, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Ramani Pichumani
  • Patent number: 7551985
    Abstract: Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: June 23, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pinhong Chen, Wilsin Gosti
  • Patent number: 7549134
    Abstract: Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ratio of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 16, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jun Li, Athanasius Spyrou, Hong Zhao, Hsien-Yen Chiu
  • Patent number: 7546360
    Abstract: A system is described in which multiple companies can securely collaborate on a design or other project, while one company can still protect certain property, such as source code, from the other collaborating companies. The system includes an inter-company collaboration system that includes a set of resources residing on a set of one or more first utility servers maintained by a first company, an access control mechanism for controlling access to the set of resources, a first data storage mechanism, and a secure network connection between the set of utility servers and a second company. The system further includes an isolated system that includes a second set of servers, a second data storage mechanism that includes a first portion that contains data shared with the collaboration system and a second portion that contains data private to the isolated system, and a second access control mechanism to control access to the second set of servers to only individuals associated with one company.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: June 9, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Anatoli G. Chiroglazov, Lawrence A. Drenan
  • Patent number: 7546562
    Abstract: In one embodiment of the invention, a physical integrated circuit (IC) design tool is provided including a design uncertainties file, a user interface (UI) software module, and a design analysis software module coupled to the UI software module, and the design uncertainties file. The design uncertainties file includes a plurality of predetermined IC design uncertainties. The UI software module communicates the plurality of predetermined IC design uncertainties to a user for selection and receives the selected IC design uncertainties from the user. The design analysis software module analyzes a circuit in response to the selected IC design uncertainties.
    Type: Grant
    Filed: November 11, 2006
    Date of Patent: June 9, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Louis K. Scheffer
  • Patent number: 7546556
    Abstract: A method of designing an electric circuit includes generating a part of the design, determining a virtual shape based on the part, and using the virtual shape to generate a design for an additional part. Design elements of the additional part, such as its size, location, or orientation for example, may be determined with the virtual shape. The method may also generate multiple virtual shapes based on the part, and may use one or more of the multiple virtual shapes to generate the next part. The method may be repeated to generate additional parts of the design using virtual shapes.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: June 9, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Todd J. Wagner