Abstract: Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design.

Abstract: Methods and systems for the integration of models and accurate predictions to score the circuit design, which translates to a more accurate and less complex yield prediction. In the present inventive approach, the computer-implemented methods and systems use at least one processor that is configured for performing at least predicting a physical realization of a layout design based at least in part on one or more model parameters, determining one or more hotspots associated with the layout design, determining a score for each of the one or more hotspots associated with the layout design, and categorizing the one or more hotspots according to at least the score in some embodiments. In some embodiments, the methods or the systems further use at least one processor for the act of determining one or more hotspots by using at least the design intent or the manufacturing information.

Abstract: A method of modeling an integrated circuit includes: specifying a layout for the integrated circuit, wherein the layout includes a plurality of devices arranged in a plurality of layers and a plurality of connections between the layers; specifying locations for a source point and an observation point for the integrated circuit; determining a plurality of static images for the source point and the observation point; determining a plurality of discrete complex images for the source point and the observation point; determining a Green's-function value for the source point and the observation point by combining the static images and the discrete complex images; and saving at least some values based on the Green's-function value.

Abstract: Disclosed are methods, systems, and computer program products for computing an exact minimal automaton to act as an intermediate assertion in assume-guarantee reasoning. In one embodiment, the computing an exact minimal automaton is performed by using a sampling approach and a Boolean satisfiability. The methods described herein may be used as part of a tool for formal verification.

Abstract: Achieving clock timing closure in designing an integrated circuit involves virtually synthesizing a clock network for the integrated circuit design to generate virtual clock buffering in the clock network before a point in the design flow at which the clock network is actually synthesized and committed to a netlist. Timing violations are determined for clock gates generated by the virtual clock buffering. Clock gating transforms are evaluated for the clock gates having the timing violations, based on recalculated clock and data path delays, to incrementally virtually synthesize the clock network. The clock gating transforms that result in the best timing gains are committed to the netlist. The clock network is then actually synthesized for the integrated circuit design, and design changes, due to the actual clock network synthesis, are committed to the netlist.

Abstract: A model library contains one or more storable models of a physical system each constructed by numerically solving relationships between a characteristic of the physical system given a set of model parameters. Such a model may be retrieved from the library according to values assigned to the model parameters and used to determine a corresponding characteristic of the physical system without repeating the numerical solution method originally used to create the model. Instead, a mapping may be applied to the storable model to seamlessly obtain the characteristic upon request.

Abstract: Disclosed is an improved method, system, and mechanism for using and constructing a minimum spanning tree. In one approach, each iteration of the process for constructing a minimum spanning tree calculates at most two additional point-pairs for nearest neighbors of points previously added to the tree. These additional point-pairs are appended to a list of point pairs, and the point-pair having the shortest distance is selected and added to the minimum spanning tree. Any metric can be employed to determine nearest neighbors, including Euclidean or Manhattan metrics. An advantage is that not all point-pairs need to be examined, greatly increasing speed and efficiency. Since every point-pair does not have to be examined, a preprocessing step is not required to reduce the number of point-pairs being considered. The resultant minimum spanning tree can be used to facilitate the routing process for an integrated circuit.

Abstract: A system and method for simulating the electrical operation of a mixed analog/digital system includes the capability for analog circuit block inputs to respond to the condition in which digital gate outputs connected to the analog circuit block input are presented in high-impedance or floating signal states, thereby providing for simulation of a wide variety of mixed analog/digital designs in which this condition occurs. In a simulated design, an analog input of one or more analog circuit blocks is transformed into an analog tri-statable input-output referred to as an ioput. The ioput is capable of driving an analog signal when the digital gate outputs connected to the analog block input are presented in a high-impedance Z state; otherwise, the ioput acts as an analog input to the analog circuit block.

Abstract: DFM systems are provided that incorporate manufacturing variations in the analysis of integrated circuits by calculating predicted manufacturing variations on the shapes of interconnects and devices of the drawn layout of a circuit design. The shape variation on interconnects is converted to variations in resistor-capacitor (RC) parasitics. The shape variation on devices is converted to variations in device parameters. The variation in device parameters and wire parasitics is converted to changes in timing performance, signal integrity, and power consumption by determining the impact of device parameter and wire parasitic variations on the behavior of each instance of a standard cell. The results from these analyses are integrated back into the design flow as incremental delay files (timing), noise failures and buffer insertion/driver resizing commands (noise), and leakage power hotspots and cell substitution commands (power consumption).

Abstract: A method of synthesis of multiple implementations of a design is provided comprising: translating a model of the design to a first output model compliant with first constraints; and translating the model of the design to a second output model compliant with second constraints.

Abstract: Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding to the RTL netlist, generating one or more low-power RTL netlists using the corresponding one or more power requirement files and the RTL netlist, and conducting low-power design explorations using the one or more low-power RTL netlists.

Abstract: A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

Abstract: Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, creating a low power gate netlist for representing a design implementation of the circuit using the RTL netlist and the power specification file, creating a reference low power RTL netlist for representing a design specification of the circuit using the RTL netlist and the power specification file, and performing equivalence checking between the low power gate netlist and the reference low power RTL netlist. The method further includes annotating low power information described in the power specification file into the reference low power RTL netlist, and creating low power logic in the reference low power RTL netlist.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: A method and a system to pre-scan a file, analyze data and create the Condensed Macro Library (CML) file. The method used is to find macros or cells of certain classes that are defined by rules. After a suitable macro or cell is identified, a parser scans the macro or cell pins and finds pins which have ports with the shapes defined on the specific layers defined by the rules and user data. Further processing is then performed based on a set of rules and the pin data to generate a CML file that contains relevant information regarding relevant pins.

Abstract: A method and system to insert redundant vias while preserving timing is disclosed. The system and method preserve the timing during redundant via insertion, which utilizes incremental timing and extraction updates. A budgeting based approach and a path based approach to the method are disclosed. The budgeting approach is faster, while the path based method has a better insight of the worst slack/slew for the entire design.

Abstract: A method and apparatus for inspection optimization is provided. Inspection optimization improves the parametric and functional yield using optimized inspection lists for in-line semiconductor manufacturing metrology and inspection equipment.

Abstract: Various embodiments of the present invention relate to a method, system, and computer program product for dynamic placement of various bond fingers on an integrated circuit (IC) package. This is achieved by determining the placement of selected bond fingers. Subsequently, bond fingers and bond wires are identified, which have been affected due to the placement of the selected bond fingers. Further, the placement of the selected and the affected bond fingers is determined based on clearance rules and the affected bond fingers and bond wires. This facilitates the dynamic placement of the various bond fingers in interaction with the user. Further, the user is provided with full interactive access and control over the method and system.

Abstract: A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or more device constraints for devices in a same room. The configuration of rooms may include a tree-structure for the rooms. The room constraints may include a common symmetry line for a first room and a second room. The device constraints may include a self-symmetry constraint for a first device about a symmetry line in a first room. The device constraints may include a symmetry constraint for a first device and a second device about a symmetry line in a first room. The devices may include analog or RF (radio frequency) devices.

Abstract: Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing the perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, the abstract flow is computed, the target locations of various electronic components to be placed are identified, the relative ordering of electronic components are determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using the incremental placement technique while minimizing the perturbation impact or the total quadratic movement of instances.