Abstract: A method of synthesis of a second circuit (N2) that is toggle equivalent to a first circuit (N1), comprising building up N2 in topological order, starting from the input side of N2, by producing a sequence of subcircuit designs N2(1) through N2(k), such that output toggling of circuit N1 implies output toggling of subcircuit N2(1) for every i=1, . . , k; and output toggling of N2(j) strictly implies output toggling of N2(i) if i<j.

Abstract: A method for synthesizing a photomask data set from a given target layout, including the following steps: (a) providing a set of target polygons for the target layout; (b) fitting a smooth curve to a target polygon of the set of target polygons, the curve having a set of etch-target points; (c) moving the etch target points according to a model of an etch process to produce a set of lithography-target points; and (d) synthesizing a photomask data set based on a model of a lithography process and the set of lithography-target points.

Abstract: A method of simulating an analog mixed-signal circuit design using mixed-language descriptions includes initializing a mixed language simulation cycle, processing digital events during delta cycles at a current simulation time of the cycle, and, after the digital events are processed, determining an analog solution at the current simulation time.

Abstract: Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.

Abstract: Behavior of a finite state machine is represented by unfolding a transition relation that represents combinational logic behavior of the finite state machine into a sequence of transition relations representing combinational logic behavior of the finite state machine in a sequence of time frames. At least one state is determined in a transition relation in the sequence that cannot be reached in a subsequent transition relation in the sequence. A subsequent transition relation in the sequence in which the at least one state cannot be reached is simplified with respect to the at least one unreachable state.

Abstract: Method and system for simulating isolation of a power domain are disclosed. The method includes receiving a netlist description of the circuit that is represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, associating the plurality of power domains and the power information specifications in the RTL design environment, where the plurality of power domains are controlled by a set of power control signals through a power manager logic, isolating a power domain among the plurality of power domains for simulation, and simulating isolation behavior of the power domain in response to variations in power applied to the power domain.

Abstract: Techniques are described which decrease DRC (design rule check) marking time, e.g., in a circuit interconnect router, by capitalizing on repetitious relationships between interconnect elements (and/or circuit components) in a circuit design, by recording previously calculated markings and reusing the markings on subsequent marking iterations or processes. Marking information corresponding to each marking point includes indications of what types of interconnect elements or circuit components can be positioned at the marking point location without violating a design rule. With a dynamic caching process, once the marking computations have been completed for an element and the corresponding points in the vicinity, those values are stored in a cache. The next time the router encounters another instance of a known element-to-point relationship, the stored values are reloaded and applied to the current point.

Abstract: Disclosed are improved methods and mechanisms for congestion and maximum flow analysis for routing an integrated circuit design. In one approach, maximum flow analysis is performed by tessellating a portion of a layout to form space tiles, which are used to interpret a flow graph. The flow graph comprises a set of vertices and edges. The capacity of edges in the flow graph is used to identify the maximum flow for that portion of the layout. In another approach, an edge walk is performed against a set of space tiles, in which a nearest neighbor determination is determined for each edge to perform maximum flow analysis.

Abstract: Systems and methods for designing integrated circuits and for creating and using androgynous interfaces between electronic components of integrated circuits are disclosed. One preferred method of designing an integrated circuit includes several steps. In one step, a foundation block for the integrated circuit is specified, including specifying the locations of multiple androgynous interfaces in the integrated circuit. In another step, one or more component blocks to comprise the integrated circuit are identified for use. In another step, the component blocks to form a layout of the integrated circuit are positioned in a manner that minimizes connection distances between functional blocks and between functional blocks and the androgynous interfaces. In another step, the androgynous interfaces are set to perform as targets (slaves) or initiators (masters) based on the layout.

Abstract: Disclosed is a method, system, and computer program product for performing interblock stitching for electronic designs. According to some approaches, interblock stitching is accomplished by implementing a stitching region between the block and external routing structures. The stitching region is implemented using local preferred direction approaches.

Abstract: An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide an IC package routing solution. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution which can include reassignment of IC nets and/or pin assignments and/or relocation of IC nets.

Abstract: First and second exposures of a mask onto a wafer are performed such that the exposure field of the second exposure partially overlaps the exposure field of the first exposure. A characteristic of a set of features is determined, and a value of a parameter of an optical proximity correction model is determined. An alignment feature can be used to align a measurement tool. In yet another embodiment, pupil intensity distribution of an imaging system is measured by exposing an image field of a radiation detector with a bright feature, positioning the detector at a distance away from the image plane, and exposing the image field of the detector with a bright feature, resulting in a cumulative exposure of the image field of the detector from the two exposures. A characteristic of a spatial pattern in the cumulative exposure of the image field of the detector is then determined.

Abstract: Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are considered as a collective object or shape, based upon the proximity of one or more of the objects to one or more other objects. The type and/or configuration of the collective object is based, for example, upon the type of rule that is being considered for the layout, placement, or routing operation.

Abstract: Method of forming a reduced model of a circuit. A circuit parameter is selected, and a plurality of values for the parameter are selected. A circuit or operator equation is solved for the selected plurality of values to generate a result. The acts of selecting parameter and its plurality of values and solving the equation are repeated to generate sufficient results to form a reduced model. For each iteration, a rank revealing factorization is performed on the matrix for use in determining whether a sufficient number of results or vectors have been generated to form the reduced model so as to form a reduced model. In the plurality of values for a selected parameter, there may exist large deviation between two of the plurality of values for a selected parameter, and such deviation need not be based upon a nominal point or deviation thereof.

Abstract: Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.

Abstract: Generating a near-minimal test pattern set for overlapping residue circuit trees in a residue network includes resolving a residue function of residue circuits through the network and making note of any gate at which the residue function thereof does not produce the assigned vector output for a given assigned set of input vectors. Where such gates cannot be resolved during one set of vector assignments, the test set that is complete up to the offending gate may be saved, and resolution of the residue function may be started from another node in the network. Multiple test sets may be generated, the combined application of which will exhaustively test each gate in the network.

Abstract: A method of synthesis of a model representing a design is provided comprising: inputting to a synthesis tool information representing a design at a level of abstraction; using a synthesis tool to automatically translate the information representing a design at a level of abstraction to a model representing the design at a lower level abstraction; and producing a record the information input to the tool representing the design at the level of abstraction.

Abstract: A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

Abstract: A method for generating timing constraint systems, where the constrained object is a digital circuit., is provided, where the constraints are generated for the use of a digital logic optimization (synthesis) tool. The synthesis tool is used to optimize the circuit, under the applied constraints, so that the circuit exhibits certain desirable timing properties, while at the same time minimizing hardware cost and various other properties. The particular class of timing constraints generated by the disclosed invention is useful when the circuit is to be retimed after optimization. Typically, the joint use of the described invention and retiming results in improvements in the overall cost/performance tradeoff curve of the design.

Abstract: The present invention relates to a method and system for tuning a circuit. In one embodiment, the method includes receiving a description of the circuit, and selecting a design point of the circuit for evaluation using a sizing tool, where the design point comprises a design of the circuit that meets a set of predefined design specifications, and the circuit comprises a group of circuit devices. The method further includes receiving a set of tuning information for the group of circuit devices tuning the group of circuit devices using the set of tuning information to create a group of tuned circuit devices, creating an updated layout of the group of tuned circuit devices using a layout tool, creating estimated parasitic information of the group of tuned circuit devices using the updated layout, and verifying the design point meets design goals of the circuit using the estimated parasitic information of the updated layout.