Patents Assigned to Cadence Design Systems
  • Patent number: 7661082
    Abstract: An apparatus and methods for the verification of digital design descriptions are provided. In an exemplary embodiment, a method of verifying a property in a digital design description is provided. The method includes deriving an abstraction of the digital design description, determining a counterexample by an approximate reachable state computation, justifying the counterexample, determining a justification frontier, updating the abstraction from the justification frontier, and producing a verification result for the digital design description. One feature of this embodiment is that it provides for efficient digital circuit verification. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 9, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Kenneth L. McMillan, Nina Amla
  • Patent number: 7661087
    Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: February 9, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
  • Patent number: 7661078
    Abstract: Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. When an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and/or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: February 9, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: David C. Noice, William Kao, Inhwan Seo, Xiaopeng Dong, Gary W. Nunn
  • Patent number: 7657856
    Abstract: Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: February 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mathew Koshy, Roland Ruehl, Min Cao, Li-Ling Ma, Eitan Cadouri, Tianhao Zhang
  • Patent number: 7657809
    Abstract: A method for testing an integrated circuit includes scanning test data from an input and an output pin into a first scan chain during a first state of a clock cycle, and scanning test data from the same input and output pins into a second scan chain during a second state of the clock cycle.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: February 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sandeep Bhatia
  • Patent number: 7657860
    Abstract: Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: February 2, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Richard Brashears, Eric Nequist
  • Patent number: 7657416
    Abstract: A method of system design, and more particularly a method of designing systems that achieve a set of performance goals using a hierarchically partitioned system representation wherein performance simulations are performed at multiple levels within the hierarchy and are combined to simulate a system level result in order to reduce the aggregate time required for performance simulation.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: February 2, 2010
    Assignee: Cadence Design Systems, Inc
    Inventors: Pero Subasic, Enis Aykut Dengi
  • Patent number: 7653890
    Abstract: A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication. The WIMAPS provides efficient processes for use by designers in predicting the RET and wafer printing process so as to allow designers to filter predict printed silicon contours prior to application of RET and printing processes to the circuit design.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: January 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Chi-Ming Tsai, Lai-Chee Man, Yao-Ting Wang, Fang-Cheng Chang
  • Patent number: 7653892
    Abstract: Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating a pattern representation based on the search pattern, defining an anchor point for the pattern representation, and assigning weights to elements of the pattern representation. The 2D IBDR can be used in systems and method for searching a design by comparing the 2D IBDR to the design. A number of 2D IBDRs can be merged into a subset of similar 2D IBDRs by characterizing desired rule geometries, sorting the 2D IBDRs into groups according to the desired rule geometries, merging the groups of 2D IBDRs into a single representative search pattern. Additionally, standard design rules can be created from the disclosed 2D IBDRs.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: January 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Frank E. Gennari, Ya-Chieh Lai, Matthew W. Moskewicz, Michael C. Lam, Gregory R. McIntyre
  • Patent number: 7653519
    Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: January 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventor: David Overhauser
  • Patent number: 7653885
    Abstract: A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: January 26, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sourav Nandy, Qi Wang
  • Patent number: 7647220
    Abstract: A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: January 12, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pawan Kulshreshtha, Robert J. Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
  • Patent number: 7644384
    Abstract: The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: January 5, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Teig, Raghu Chalasani, Akira Fujimura
  • Patent number: 7644380
    Abstract: Method for analyzing a circuit composed of MOS devices. The method can be used to direct MOS devices in static and dynamic circuits and involves identifying an undirected MOS device that connects nets. Functions of the nets that cause each net to be logic values are defined as a function of inputs to the circuit. The defined functions can include pulldown functions or both pullup and pulldown functions. A set of rules is used to determine the direction of a signal that flows through a device and applies defined functions. The rules for analyzing static devices may differ from the rules for analyzing dynamic devices. Devices that are determined to have uni-directional signal flow can be directed. Additionally, devices having bi-directional signal flow and uni-directional observability can be directed.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: January 5, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Samuel L. Kerner, Chih-chang Lin
  • Publication number: 20090319976
    Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).
    Type: Application
    Filed: June 23, 2009
    Publication date: December 24, 2009
    Applicant: Cadence Design Systems, Inc.
    Inventors: Ming Liu, JenPin Weng, Taber Smith
  • Patent number: 7634743
    Abstract: Method for updating a circuit design. A modification to a netlist that includes original components and original spare cells is received. Original components that are not required by the modification are identified, disconnected and marked or made new spare cells. A pool of spare cells is generated and includes original and new spare cells. The netlist is updated by adding new components, and added components are mapped to spare cells selected from the pool. If mapping does not satisfy a design constraint, such as a timing constraint, then original components can be de-mapped and made spare cells, added components are mapped to spare cells resulting from de-mapping, and de-mapped components can be re-mapped to other spare cells.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: December 15, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Arnold Ginetti
  • Patent number: 7634038
    Abstract: A self-tuning 3rd order type III phase-locked loop (PLL) is disclosed. In one aspect, the PLL provides frequency control that is implemented in three (3) parallel paths. The PLL provides frequency response tracking using a number of elements including a triple control voltage-controlled oscillator (VCO), a frequency-to-current (F2I) converter, and a switched capacitor loop filter. In addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched capacitor filters synchronized to a reference signal, near constant VCO gain over process variations allows the open loop frequency response to be tailored to track the reference signal. A high-speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL may be fabricated in a 0.18 ?m CMOS logic process.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: December 15, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael Hufford, Eric Naviasky, Stephen Williams, Michelle Williams
  • Patent number: 7634749
    Abstract: A method of designing a skew insensitive circuit is performed by designing a synchronous circuit including flip-flops and combinatorial logic and, for each flip-flop, inserting logic gates to receive a skewed clock signal and to locally derive non-overlapping clock phases from the skewed clock signal.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: December 15, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jordi Cortadella, Alex Kondratyev, Luciano Lavagno
  • Patent number: 7631283
    Abstract: A method for producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other embodiments provide a method for locating vias in the power grid structure in such a way as to be especially beneficial to 45° or 135° diagonal wiring paths. The method includes processes of a power grid planner, power grid router, power grid verifier, and global signal router that are used iteratively to define and produce a power grid structure. Other embodiments of the invention provide for arrangements of vias in via arrays where diagonal wiring paths are facilitated near the edges of the via arrays. A bounding box enclosing these via arrays have an aspect ratio that is approximately equal to 1.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: December 8, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Hengfu Hsu
  • Patent number: 7631289
    Abstract: Disclosed is an improved method and system for creating lithography models. According to some approaches, a new method and system is disclosed for determining the number of matrices to use for representing an optical lithographic model. The approach is based upon a selected accuracy level, instead of requiring the user to select the number of matrices that is desired as was employed in the prior art. The method and system will then determine the number of matrices to use to support the accuracy that is desired.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: December 8, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventor: Junjiang Lei