Abstract: A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.

Abstract: A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.

Abstract: Disclosed three-dimensional stacked package structure includes: a packaging substrate, having a substrate body, connecting leads, a through-hole penetrating the substrate body, a first pad and a second pad on opposite surfaces of the substrate body. The stacked structure on the first surface of the substrate body includes a second storage block, and a first storage block above the second storage block; the connecting leads include a first lead and a second lead with equal lengths, the first lead is above the package substrate, and one end is electrically connected to the first pad, and the other end is electrically connected to the first storage block. The second lead passes through the through-hole, and one end is electrically connected to the second storage block, the other end is electrically connected to the second pad. The present disclosure reduces the crosstalk between signal lines, thereby reducing signal delay between different storage blocks.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an active pillar including a channel region and a source/drain region arranged on two sides of the channel region; and a gate structure surrounding at least part of the channel region. The channel region includes a peripheral portion and a central portion, the peripheral portion is positioned between the gate structure and the central portion, the source/drain region and the peripheral portion have a first doping type, and the central portion has a second doping type, where the first doping type is one of N-type and P-type, and the second doping type is other one of the N-type and the P-type. At least problems of greater difficulty in turning off existing junctionless field effect transistor and poorer turn-off effect may be solved.

Abstract: A preparation method of the semiconductor structure includes: the substrate including a first area to be etched and a second area to be etched outside the first area to be etched, the etching rate of the first area to be etched and the second area to be etched are different, simultaneously etching the first area to be etched and the second area to be etched at least twice, until an etching depth of one of the first area to be etched and the second area to be etched with a less etching rate is equal to a target etching depth; in at least two etching processes, backfilling a sacrificial material to the first area to be etched and the second area to be etched after a previous etching is completed, removing part of the sacrificial material in a next etching.

Abstract: A method for manufacturing a memory includes: providing a substrate provided with bit lines, each bit line including a plurality of straight line segments connected end to end in sequence, and adjacent straight line segments have an included angle therebetween; forming active pillars and insulating layers on the substrate, each straight line segment of each bit line being electrically connected with at least two active pillars, each insulating layer extending in a first direction and covering the outer peripheral surface of the active pillar; filling a first support layer between adjacent insulating layers; removing part away from the substrate, of each insulating layer to form a filling space; and forming a dielectric layer and a conductive layer between parts exposed in the filling space and close to the substrate, of the active pillars.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure provided by the present disclosure includes: providing a substrate; forming a base pattern on the substrate, where the base pattern includes a plurality of bit lines arranged in parallel, and an isolation structure is disposed between adjacent two of the bit lines; forming a plurality of semiconductor pillars arranged in a direction of the bit line on a surface of each of the bit lines, where the bit line is electrically connected to the semiconductor pillar; forming a gate-all-around structure on a surface of the semiconductor pillar, where the gate-all-around structure includes a first insulating layer, a gate structure layer, and a second insulating layer that are sequentially disposed on a side surface of the semiconductor pillar.

Abstract: A semiconductor structure includes a base, a chip stack located on the base, and first conductive structures. The chip stack includes chips stacked in sequence in a direction perpendicular to a plane of the base, a chip includes first and second sub-portions, a first surface of the first sub-portion is flush with that of the second sub-portion, a second surface of the first sub-portion protrudes from that of the second sub-portion, and the first and second surfaces are oppositely arranged. A first conductive structure includes a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and the materials of the first conductive bump and the first through-silicon via are same.

Abstract: A read/write switching circuit and a memory are provided. The read/write switching circuit includes: a first data line (Ldat) connected to a bit line (BL) through a column select module, a first complementary data line (Ldat #) connected to a complementary bit line through the column select module, a second data line (Gdat) and a second complementary data line (Gdat #), and further includes: a read/write switching module (101) configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line (Ldat #) and the second complementary data line (Gdat #)during read and write operations in response to read and write control signals; and an amplification module (102) connected between the first data line (Ldat) and the first complementary data line (Ldat #) and configured to amplify data of the first data line (Ldat) and data of the first complementary data line (Ldat #).

Abstract: A method for forming a semiconductor structure includes the following operations. A substrate is provided and includes a stacked structure and a first isolation structure that are alternately arranged in a first direction. A grid-like etched groove extending in the first direction is formed in the stacked structure and the first isolation structure, and divides the substrate into a first region and a second region that are arranged sequentially in a second direction. The first direction and the second direction are any two directions in a plane where the substrate is located. A second isolation structure is formed in the grid-like etched groove. A transistor structure and a capacitor structure are respectively formed in the first region and the second region, and are isolated by the second isolation structure.

Abstract: A method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory are provided. The method includes: a substrate is provided; a stack structure is formed on the substrate; the stack structure is divided into multiple channel areas, first source-drain areas and second source-drain areas. Each channel area extends in a second direction, each first source-drain area and each second source-drain area extend in a first direction, and the first source-drain area and the second source-drain area are located on the same side of the channel area; a first source-drain structure extending in the first direction is formed in the first source-drain area and a second source-drain structure extending in the first direction is formed in the second source-drain area; and a channel structure extending in the second direction is formed in the channel area.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, bit line structures, and an isolation structure. The substrate includes multiple active areas. The bit line structures are located above the active areas, and include multiple bit lines extending in a first direction parallel to the surface of the substrate and multiple contact plugs electrically connected to the bit lines and the active areas. The isolation structure includes a first insulating layer including a first part and a second part located below the first part, a second insulating layer covering the surface of the second part and a third insulating layer covering at least the surface of the first part. The first part covers at least side walls of the bit lines, and the second part covers at least side walls of the contact plugs.

Abstract: A semiconductor package includes a first base plate, first semiconductor structure, second base plate and filling layer. The first base plate has a first surface including first and second signal transmission regions. The first semiconductor structure located on the first surface is electrically connected to the first signal transmission region. The second base plate located on the first base plate includes a base and a first interconnection surface. The first interconnection surface is away from the first surface. The first interconnection surface has first and second interconnection regions communicated with each other. The first interconnection region is electrically connected to the second signal transmission region. The filling layer seals the first semiconductor structure, second base plate and first surface. The first interconnection region is not sealed, and the second interconnection region is. There is a preset height between a top surface of the filling layer and the first interconnection region.

Abstract: A package structure includes at least two semiconductor structures that are stacked onto one another. The first surface of one semiconductor structure of the at least two semiconductor structures that are stacked onto one another directly faces toward the second surface of another semiconductor structure of the at least two semiconductor structures which is adjacent to said one semiconductor structure; the first metal layer of said one semiconductor structure is in contact with and bonded to the third metal layer of said another semiconductor structure; and the second metal layer of said one semiconductor structure is in contact with and bonded to the fourth metal layer of said another semiconductor structure.

Abstract: A method for manufacturing a semiconductor device includes following operations. A substrate is provided, including memory array region. A plurality of bit lines are formed in memory array region. First insulating material is filled between the plurality of bit lines. A plurality of trenches intersecting with bit lines are provided in first insulating material. Memory array region includes inner region and boundary region outside same. Second insulating material is filled in trenches to form spacing lines. Second insulating material is also deposited above bit lines, spacing lines and first insulating material to form cap material layer. Etching process is performed to form node contact holes, including following operations. Cap material layer is etched to form cap layer covering bit lines, spacing lines and first insulating material in boundary region. First insulating material in inner region is removed by etching with cap layer as mask to from node contact holes.

Abstract: A refresh control method includes: generating a first random number; and preforming, in response to execution times of a regular refresh operation reaching the first random number after execution of a previous row hammer refresh operation, a new row hammer refresh operation.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a switching transistor and a storage transistor. The switching transistor includes a first gate electrode, a first channel layer coating a portion of the first gate electrode, and a first source-drain electrode and a second source-drain electrode both covering a surface of the first channel layer. The storage transistor includes a second gate electrode, a second channel layer coating a portion of the second gate electrode, and a third source-drain electrode and a fourth source-drain electrode both covering a surface of the second channel layer. A portion of the second gate electrode extending out of the second channel layer in a first direction is electrically connected to the second source-drain electrode. The storage transistor is configured to store charge.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; and a stack structure arranged on the substrate. The stack structure includes storage areas spaced apart from each other in a first direction, and isolation walls, each isolation wall being arranged between any two adjacent storage areas of the storage areas. Each storage area includes memory cells spaced apart from each other in a second direction, each memory cell including a transistor structure, and a capacitor structure, an outline of a projection of the capacitor structure on a top surface of the substrate being in a shape of a rectangle or a rounded rectangle. A width of the transistor structure is equal to a width of the capacitor structure in the first direction, and the transistor structure is aligned with the capacitor structure in the third direction.

Abstract: Embodiments provide a semiconductor structure and a method thereof. The method includes: providing a first substrate, and forming a drive pad on the first substrate; providing a second substrate, and forming active pillars and a bit line in sequence on a side of the second substrate, wherein a side of the bit line is connected to the active pillars, and a surface of the bit line facing away from the active pillars is exposed on a surface of the second substrate; bonding the bit line to the drive pad correspondingly; thinning the second substrate from a side of the second substrate facing away from the first substrate until the active pillars are exposed; and forming a storage capacitor on sides of the active pillars facing away from the drive pad, the storage capacitor being connected to the active pillars.

Abstract: A semiconductor package assembly and a manufacturing method are provided. The semiconductor package assembly includes: a base plate having a first surface; a first chip structure located on the base plate and electrically connected to the first surface of the base plate; an intermediary layer having a first interconnection surface; and a molding compound. The first interconnection surface has a first and second interconnection regions. A first solder ball is formed on the first interconnection region. A first pad is formed on the second interconnection region. The intermediary layer is electrically connected to the first surface by means of the first pad. The molding compound seals the first chip structure, the intermediary layer and the first surface. The first solder ball has a surface exposed from the molding compound. There is a preset height between the exposed surface of the first solder ball and the first interconnection surface.