Abstract: The present disclosure relates to the technical field of semiconductors, and provides a memory device, and a semiconductor structure and a forming method thereof. The forming method includes: providing a substrate, where the substrate includes a source region and a drain region spaced apart from each other, and a gate trench located between the source region and the drain region; forming, in sequence on an inner wall of the gate trench, a gate oxide layer, an interface layer, and a conductive layer that fills the gate trench; and etching back the side of the interface layer away from the bottom of the gate trench by using a wet etching process, such that a top height of the interface layer is lower than a top height of the conductive layer.

Abstract: Embodiments provide a memory structure, including: a capacitive structure, provided with an upper electrode layer; a conductive column, arranged on the upper electrode layer, and in contact with and electrically connected to the upper electrode layer; a metal layer, arranged on a side of the conductive column away from the upper electrode layer, the conductive column being in contact with a surface of the metal layer facing the upper electrode layer; and at least one buffer column, spaced apart from the conductive column, in contact with the surface of the metal layer facing the upper electrode layer, and extending in a direction from the metal layer to the upper electrode layer.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a base; forming a bottom electrode layer on the base, wherein a crystal structure of the bottom electrode layer includes a tetragonal crystal system; forming a first dielectric layer on a surface of the bottom electrode layer by using the bottom electrode layer as a seed layer, wherein a crystal structure of the first dielectric layer includes a tetragonal crystal system; and forming a first current blocking layer on a surface of the first dielectric layer.

Abstract: Embodiments of the present disclosure provide a film and a forming method thereof. The forming method includes: providing a base; forming a diamond-like carbon film on the base, where the DLC film has carbon-hydrogen chemical bonds; and performing photocatalytic treatment on the DLC film, to break at least some of the carbon-hydrogen chemical bonds and reduce content of hydrogen elements in the DLC film.

Abstract: A package substrate and a semiconductor structure with the package substrate are provided. The package substrate includes a body and a conductive layer. The body includes an opening region. The conductive layer is disposed at the opening region. The conductive layer includes a first conductive bridge and a second conductive bridge. The first conductive bridge and the second conductive bridge are disposed at intervals. The first conductive bridge is provided with at least one first via. The first conductive bridge and the second conductive bridge are disposed at intervals in the opening region.

Abstract: Embodiments of the present application provide a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes: providing a substrate, a dielectric layer on the substrate, the dielectric layer having a trench; forming a metallic copper layer filling the trench; forming a contact layer on an upper surface of the metallic copper layer, a material of the contact layer containing cuprous ions; and forming a barrier layer on an upper surface of the contact layer, a material of the barrier layer containing a same element as the material of the contact layer. The embodiments of the present application help improve a contact effect between the metallic copper layer and the barrier layer.

Abstract: A semiconductor structure includes: a substrate, a conductive pattern layer, a support layer and a re-distribution layer. The conductive pattern layer is arranged on the substrate. The support layer covers the conductive pattern layer and is provided with a via hole. The re-distribution layer is arranged on the support, and the re-distribution layer includes a test pad at least located in the via hole. The test pad includes a plurality of test contact portions and a plurality of recesses that are arranged alternately and connected mutually, and the recess is in corresponding contact with a portion of the conductive pattern layer in the via hole.

Abstract: Embodiments of the disclosure disclose a semiconductor device and a method manufacturing thereof. The semiconductor device includes a substrate as well as a first groove and a second groove located in the substrate, in which the second groove is formed by etching the substrate downwards from part of a bottom surface of the first groove, and a sidewall of the second groove retracts inward by a preset length relative to a sidewall of the first groove; a word layer including a first sub-portion located in the second groove and a second sub-portion located in the first groove, in which a gap is provided between a sidewall of the second sub-portion and that of the first groove; and a word line cover layer located in the first groove and covering the second sub-portion, in which an air gap structure at least located at the gap is provided in the word line cover layer.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a support layer located on the substrate, wherein the support layer includes a first support segment and a second support segment, the first support segment and the second support segment are both connected to the bit line, and the bit line is located between the first support segment and the second support segment.

Abstract: The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.

Abstract: A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate, a trench and a word line. The substrate includes an isolation structure and an active area. The active area includes irons of a first type. The trench is arranged in the active area, an inner surface of the trench includes an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer is arranged above the oxide layer. The word line is arranged in the trench. The inversion doping layer includes ions of a second type. The first type is contrary to the second type.

Abstract: A gas pressure balance valve includes a valve body, a one-way valve and a buffer assembly. The valve body includes a gas inlet end and a gas outlet end, the gas inlet end is connected with a first gas pressure area, the gas outlet end is connected with a second gas pressure area, and a pressure difference is existed between the first gas pressure area and the second gas pressure area. The one-way valve is located in the valve body, and configured to achieve the balance between the pressures of the first gas pressure area and the second gas pressure area. The buffer assembly is located between the gas inlet end and the one-way valve, and configured to adjust the pressure on the surface of the one-way valve.

Abstract: An overhead traveling vehicle and an overhead traveling vehicle fault processing system are provided. The overhead traveling vehicle includes: an overhead traveling vehicle main body; a main walking part, installed on the overhead traveling vehicle main body and configured to drive the overhead traveling vehicle main body to walk on tracks; an auxiliary walking part, installed on the overhead traveling vehicle main body and configured to drive the overhead traveling vehicle main body to walk on the tracks; and a control part, configured to control one of the main walking part and the auxiliary walking part to be on the tracks and to control the other one of the main walking part and the auxiliary walking part to leave the tracks.

Abstract: A word line driver includes a PMOS area, a NMOS area, first gates, and second gates. The PMOS area includes first active areas extending along a first direction. The first active area includes a first channel area, a first source area and a first drain area. The NMOS area includes second active areas. The second active area includes a second channel area, a second source area, a second drain area, a third channel area, a third source area, and a third drain area. The extension direction of the first gate corresponding to the first active area is inclined compared with the first direction. The second gate covers the third channel area. The second gate, the third source area and the third drain area constitute a holding transistor.

Abstract: The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.

Abstract: The present disclosure relates to a method for manufacturing a semiconductor structure, the method includes: a substrate is provided; a bit line array is formed on an upper surface of the substrate, the bit line array includes several bit lines arranged at intervals, the bit lines are connected through at least one support pattern, and the at least one support pattern penetrates through the bit line array along an arrangement direction of the bit lines; a bit line side wall is formed on side walls of each of the bit lines; a part of the at least one support pattern is removed so as to expose at least one sacrificial layer; and the at least one sacrificial layer is removed, so as to form at least one air gap between the first side wall dielectric layers and the second side wall dielectric layers.

Abstract: A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay circuit configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch circuit configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.

Abstract: Embodiments provide a storage system, including: a basis chip and memory chips, where the memory chip includes memory cells, the storage system has channels, each of the channels includes a partial number of memory cells in all the memory chips, a partial region of each of the channels corresponds to one memory chip, and each channel is electrically connected to the basis chip; and a temperature processing circuit configured to obtain first temperature codes corresponding to the memory chips, to obtain a second temperature code representing a temperature of the basis chip, and to compare the first temperature codes with the second temperature code to output a high temperature representation code, where the first temperature code represents a maximum temperature in the partial regions of all the channels, and the high temperature representation code is one of the first temperature codes or the second temperature code representing a higher temperature.

Abstract: A forming method for a semiconductor structure and the semiconductor structure are provided. The forming method of the semiconductor structure includes: providing a substrate, wherein separate bit line structures are formed on the substrate; forming a first sacrificial layer on a sidewall of a bit line structure; forming first dielectric layer filling gaps between adjacent bit line structures; patterning a first dielectric layer to form vias, wherein the vias expose active regions of the substrate, and the vias and remaining parts of the first dielectric layers are alternately arranged in an extension direction of the bit line structures; forming a second sacrificial layer on sidewalls of a via, and filling the via to form a contact plugs; forming a contact structure on the contact plug; and removing the first sacrificial layer to form first air gap, and removing the second sacrificial layer to form a second air gap.