Abstract: A semiconductor package assembly and a manufacturing method are provided. The semiconductor package assembly includes: a base plate having a first surface; a first chip structure located on the base plate and electrically connected to the first surface of the base plate; an intermediary layer having a first interconnection surface; and a molding compound. The first interconnection surface has a first and second interconnection regions. A first solder ball is formed on the first interconnection region. A first pad is formed on the second interconnection region. The intermediary layer is electrically connected to the first surface by means of the first pad. The molding compound seals the first chip structure, the intermediary layer and the first surface. The first solder ball has a surface exposed from the molding compound. There is a preset height between the exposed surface of the first solder ball and the first interconnection surface.

Abstract: Embodiments of the present disclosure relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, first gates and second gates, and a first conductive channel; where the substrate includes first active regions and two second active regions located between adjacent first active regions, the first active region defines a pull-down transistor, the second active region defines a pull-up transistor; the first active region has a first source region, a first channel region, and a first drain region arranged along a second direction.

Abstract: A capacitor structure includes a substrate and a first electrode, a first dielectric layer and a second electrode arranged on the substrate, in which the first electrode includes at least two sub-electrodes continuously arranged in a direction perpendicular to the substrate and connected in sequence, of the at least two sub-electrodes, an orthographic projection of at least one of the sub-electrodes on the substrate covers an orthographic projection of another of the sub-electrodes on the substrate; the first dielectric layer is arranged on at least part of an outer surface of the first electrode; the second electrode is arranged on at least part of an outer surface of the first dielectric layer, and the second electrode is insulated from the first electrode.

Abstract: Disclosed in the embodiments of the disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure includes: a substrate; a plurality of grooves, located in the substrate and extending in a first direction; a plurality of word line structures, located in the grooves; and a plurality of semiconductor layers, each at least partially located between a word line structure and an inner wall of a groove. The semiconductor layer includes oxide semiconductor material.

Abstract: A semiconductor structure and a memory are provided. The semiconductor structure includes multiple active regions, a column selector and multiple bit lines. The column selector includes a first gate, a second gate, a third gate, a fourth gate and a connection line. The first gate and the second gate intersect at a first node, the third gate and the fourth gate intersect at the second node, and the connection line connects the first node and the second node. Each of the multiple bit lines includes a first portion, a second portion and a connection portion. Each of the multiple bit lines is connected to a respective one of the multiple active regions, the active regions connected to different bit lines among the multiple bit lines are different.

Abstract: A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.

Abstract: A method of forming a semiconductor structure and a semiconductor structure are provided. The method of forming the semiconductor structure includes: providing a base, where the base includes a first dielectric layer and pads arranged at intervals in the first dielectric layer; forming a dielectric structure, where the dielectric structure exposes the pad and part of the first dielectric layer; forming an insulating structure, where the insulating structure is formed on a sidewall of the dielectric structure, the insulating structure covers a first partial sidewall of the dielectric structure, and an air gap is formed between a second partial sidewall of the dielectric structure and the insulating structure; and forming a conductive structure, where the conductive structure covers an exposed pad and an outer sidewall surface of the insulating structure.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate; a plurality of capacitors arranged in the substrate; and a plurality of active pillars arranged above the substrate. Each of the plurality of active pillars is arranged above a respective one of the plurality of capacitors, and a bottom portion of each of the plurality of active pillars is electrically connected to a top portion of the respective one of the plurality of capacitors therebelow.

Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: Embodiments are a method for fabricating a semiconductor structure. The method includes: providing a substrate; etching the substrate to form bit line grooves extending along a first direction; sequentially forming a first isolation layer, a bit line metal line layer, a bit line conductive connection layer and a first insulating layer to obtain a bit line structure; etching to form a substrate of the bit line structure, and to obtain a plurality of active area structures arranged at intervals and a first groove, the bit line structure intersecting with the active area structures; filling the first groove with a second isolation layer to obtain a first structure; etching the first structure to form word line grooves extending along a direction perpendicular to the first direction; and sequentially forming a third isolation layer, a word line conductive connection layer and a second insulating layer in the word line groove.

Abstract: The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.

Abstract: Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.

Abstract: A semiconductor structure includes a substrate and a phase-change memory cell located on the substrate. The phase-change memory cell includes a phase-change material layer and a heating layer. The heating layer is located between the phase-change material layer and the substrate, and includes a first portion composed of a first conductive material and a second portion composed of a second conductive material. The first portion surrounds at least a sidewall of the second portion.

Abstract: A semiconductor structure and a method of fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a carrying layer, a barrier layer, a solder layer and an adhesive layer. The barrier layer is located on the surface of the carrying layer, and there are openings in the barrier layer. The barrier layer includes multiple sub-barrier layers in a stack. The multiple sub-barrier layers respectively form a plurality of steps in the opening, and the heights of the plurality of steps decrease sequentially in a direction from outside of the opening to inside of the opening. A solder layer and an adhesive layer are located in the opening, and the adhesive layer covers the solder layer.

Abstract: A method for manufacturing a semiconductor structure includes: a base provided with a contact hole is provided; an initial contact structure including a first diffusion barrier layer, a conductive layer and a second diffusion barrier layer stacked onto one another is formed on the base, the first diffusion barrier layer conformably covering the contact hole and covering part of a top surface of the base, the conductive layer covering first diffusion barrier layer and being filled in unoccupied space in the contact hole, the second diffusion barrier layer covering a side of the conductive layer away from first diffusion barrier layer, the initial contact structure outside the contact hole being provided with a groove exposing side walls of conductive layer and second diffusion barrier layer; a third diffusion barrier layer is formed on a side wall of initial contact structure exposed by the groove to obtain a target contact structure.

Abstract: A semiconductor memory, a refresh method and an electronic device are provided. The semiconductor memory includes a main storage area and a mark storage area, multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event.

Abstract: This invention relates to a semiconductor structure and a fabrication method therefor. The method for fabricating a semiconductor structure includes: providing a substrate, where a shallow trench isolation structure is formed on the substrate; forming a plurality of transistor accommodating grooves in the active regions, where there is a spacing between the transistor accommodating groove and the shallow trench isolation structure; forming a columnar structure in the transistor accommodating groove, where the columnar structure includes a source, a conductive channel, and a drain that are sequentially disposed in a direction away from the substrate; etching the active region located within the spacing and the active region located between adjacent columnar structures in the same active region to form a bit line trench, where the bit line trench surrounds the source; and forming a bit line that surrounds and connects the source in the bit line trench.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, including: a first base, the first base includes a bit line, a transistor, and a first contact structure that are stacked; and a second base, bonded with the first base, the second base includes a second contact structure and a capacitor that are stacked, and the second contact structure is in contact with the first contact structure in an aligned manner; the first contact structure has a first surface facing the second base and a second surface opposite to the first surface, and an area of the first surface is larger than an area of the second surface; and the second contact structure has a third surface facing the first base and a fourth surface opposite to the third surface, and an area of the third surface is larger than an area of the fourth surface.

Abstract: The present disclosure discloses a memory and a manufacturing method thereof. The memory includes: active regions extending in a first direction and word lines extending in a second direction, wherein each of the word lines is partially located between adjacent active regions; the word line includes a gate conductive layer; and, in a direction parallel to the first direction, each of the active regions has an end face facing the word lines, and an extreme difference in distances between the end face and the gate conductive layer is within a preset range.

Abstract: The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.