Abstract: Method for forming a capacitor includes following operations. A base is provided. First supporting layer and first sacrificial layer are formed on the base sequentially. First through holes penetrating first supporting layer and first sacrificial layer are formed to expose the base. First through holes are filled to form first filling structures. Second supporting layer covering remaining first sacrificial layer and first filling structures is formed. Second through holes penetrating second supporting layer are formed. Second sacrificial layer covering remaining second supporting layer and second through holes, and third supporting layer are formed. Third through holes penetrating third supporting layer and second sacrificial layer are formed. First filling structures are removed to communicate each of third through holes and corresponding one of first through holes.

Abstract: A method for manufacturing a fin transistor structure includes the following: a substrate is provided, a fin part protruding from a top surface of the substrate; an isolation layer is formed on the substrate, a top surface of the isolation layer being lower than a top of the fin part, so that an upper part of the fin part is exposed above the isolation layer; and doping processing is performed on the upper part of the fin part by a diffusion process to form at least one of a source region or a drain region in the upper part of the fin part.

Abstract: A semiconductor structure includes a substrate and a word line (WL) structure. The WL structure includes: a work function stacking structure located in the substrate, where the work function stacking structure includes multiple sequentially and alternately stacked first work function layers and second work function layers, and a work function of the first work function layer is greater than a work function of the second work function layer; a WL conductive layer located in the substrate, and located on an upper surface of the work function stacking structure; and a gate oxide layer located between the work function stacking structure and the substrate as well as between the WL conductive layer and the substrate.

Abstract: Disclosed is a semiconductor device. The semiconductor device includes: a substrate, including a first surface and a second surface opposite to each other; a gate, located on the first surface of the substrate; a source region located in the substrate on one side of the gate and a drain region located in the substrate another side of the gate; and an anti-punchthrough structure located in the substrate and including a third surface and a fourth surface opposite to each other. The third surface is adjacent to the first surface and lower than the first surface, and the anti-punchthrough structure is located between the source region and the drain region.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes a plurality of active pillars, a dielectric layer that is disposed around a circumference of the active pillar and that covers a part of a sidewall of the active pillar, and a word line. Any two adjacent ones of the plurality of active pillars are separated by using a first trench or a second trench. The first trench and the second trench are staggered. The second trench is wider than the first trench. The dielectric layer is disposed around the circumference of the active pillars. The word line partially covers the dielectric layer, and fills a part of the first trench located between adjacent active pillars.

Abstract: The present disclosure relates to the technical field of semiconductors and provides a semiconductor structure, a method of forming same, and a memory. The method of forming a semiconductor structure of the present disclosure includes: providing a carrier board; forming a chipset on one side of the carrier board, where the chipset includes multiple chips stacked in a direction perpendicular to the carrier board; where among multiple chips, an orthographic projection of a chip closer to the carrier board on the carrier board is within an orthographic projection of a chip farthest from the carrier board on the carrier board; forming an insulating dielectric layer covering the chipset; and performing a grinding process to expose a predetermined surface of the chip farthest from the carrier board outside the insulating dielectric layer.

Abstract: Embodiments relate to a method and an apparatus for analog simulation of a circuit model. The method includes: obtaining a plurality of different environment variable values of the circuit model; obtaining delay time of each of the logic devices in the oscillator under the plurality of different environment variable values according to the plurality of environment variable values; inputting the delay time of each of the logic devices in the oscillator under the plurality of different environment variable values into the digital circuit model to perform a simulation test; obtaining frequencies of an output signal from the oscillator under the plurality of different environment variable values; and obtaining a relationship between the plurality of environment variable values and the frequencies of the output signal from the oscillator according to the frequencies of the output signal from the oscillator under the different environment variable values, to digitize the environment variable values.

Abstract: Embodiments of the disclosure relate to the semiconductor field, and provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate that has a bit line extending in a first direction; an active pillar located on the bit line, in which a bottom surface of the active pillar is in contact with the bit line, and the active pillar is doped with an N-type element; an inversion region located on the side surface of the active pillar, and doped with a P-type element; a dielectric layer and a word line extending in a second direction, in which the dielectric layer and the word line wrap part of the inversion region, and the dielectric layer is located between the word line and the inversion region.

Abstract: The method for forming the capacitor stack structure includes: providing a substrate on which a plurality of first laminated structures arranged in a first direction and a first isolation structure located between every two adjacent the first laminated structures are formed, and the first laminated structure including first semiconductor layers and second semiconductor layers stacked alternately; forming, in the first laminated structures and the first isolation structures, first trench extending in the first direction, the spacing in a second direction between the adjacent remaining first semiconductor layers is greater than the spacing between the adjacent remaining second semiconductor layers; forming a support structure in the first trench, and removing the first semiconductor layers from the first laminated structure to form a first space; and forming capacitor structures in the first space to form a capacitor stack structure.

Abstract: Semiconductor structure and forming method therefor are provided. The semiconductor structure includes: substrate; first vertical transistor, including first source, first channel region located on the first source, first drain located on the first channel region, and first gate dielectric layer and first gate surrounding the first channel region; first storage structure located on the first drain; second vertical transistor, including the first source, second channel region located on the first source, second drain located on the second channel region, and second gate dielectric layer and second gate surrounding the second channel region; and second storage structure located on the second drain. The first source has bottom structure, first connection structure connecting the bottom structure, the first channel region and the second channel region, and second connection structure connecting the bottom structure and located on two sides of the first channel region and the second channel region.

Abstract: A semiconductor structure, a method for forming a semiconductor structure, and a memory are provided. The method for forming the semiconductor structure in the disclosure includes: providing a base, the base including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart from each other in a first direction, and the insulating dielectric layer being filled in each of the plurality of first trenches; patterning and etching the base to form a plurality of second trenches spaced apart from each other in a second direction, the second direction intersecting with the first direction; forming a word line structure in each of the plurality of second trenches; forming an air gap between each two adjacent word line structures of a plurality of word line structures; and sealing the air gap.

Abstract: A semiconductor device includes a substrate including a memory region and a peripheral region located at an outer side of the memory region; a memory structure located above the memory region and including a memory array and signal lines, the memory array at least including memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, the first direction is perpendicular to the top surface of the substrate; a peripheral structure located above the peripheral region and including peripheral stacked layers, peripheral circuits located above the peripheral stacked layer, and peripheral leads located above the peripheral circuits, one end of each peripheral lead being electrically connected with at least one of peripheral circuits, and the other end being electrically connected with at least one of signal lines.

Abstract: A semiconductor structure and a method for forming semiconductor structure are provided. The method includes: after a plurality of capacitor vias are formed in a support layer and a sacrifice layer, external electrode layers are formed on sidewall surfaces of the capacitor vias; a dielectric layer is formed on a sidewall surface of each external electrode layer; remaining sacrifice layer between the external electrode layers is removed to form a cavity at a position where remaining sacrifice layer has been removed; an internal electrode layer is formed on a surface of the dielectric layer and a bottom surface of each capacitor via; a first conductive layer completely filling the cavity is formed, where the first conductive layer is in contact with a respective one of the external electrode layers; and a second conductive layer completely filling a remaining part of each capacitor via is formed on the internal electrode layer.

Abstract: A storage device and a method for forming a storage device are provided. The storage device includes: a semiconductor substrate, active areas being formed in the semiconductor substrate, and spaced apart from each other by first trenches and second trenches extending along a first direction and third trenches extending along a second direction; a bit line doped area arranged at a bottom portion of each second trench and at a bottom portion of a communication region of each third trench with each second trench; a first isolation layer arranged in each first trench and each third trench; a gate dielectric layer arranged on surfaces of the active areas and surrounding the active areas; metal gates arranged on a surface of the gate dielectric layer on side walls of the active areas and surrounding the active areas; and a source area arranged on a top surface of each active area.

Abstract: A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

Abstract: A semiconductor package structure includes: a first base plate provided with a first surface; a first chip stack body located on the first base plate, where the first chip stack body includes a plurality of first semiconductor chips successively stacked onto one another in a direction perpendicular to the first base plate, and is electrically connected to the first surface of the first base plate; an interposer layer located on the chip stack body and provided with a first interconnection surface, where the first interconnection surface is provided with a first interconnection region electrically connected to the first base plate and a second interconnection region; and a molding layer configured to seal the first chip stack body, the interposer layer and the first surface of the first base plate. The first interconnection region is unsealed by the molding layer, and the second interconnection region is sealed by the molding layer.

Abstract: Provided are semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a first base; a first semiconductor chip connected to the first base; a second semiconductor chip stack structure located on the first semiconductor chip, the second semiconductor chip stack structure including a plurality of second semiconductor chips stacked in sequence in a first direction, the second semiconductor chip stack structure being provided with a plurality of first leads on an outermost side of the second semiconductor chips in the first direction, in which the first direction is a direction parallel to a plane of the first base; and at least one second base, signal lines in the at least one second base being connected to the first leads, the at least one second base being connected to the first base in a direction perpendicular to the plane of the first base.

Abstract: A method for manufacturing method semiconductor includes: providing a base; forming an annular sacrificial blocking layer in the base; forming an etched hole in the base, in which the etched hole is located at an inner side of the annular sacrificial blocking layer; and removing the annular sacrificial blocking layer to obtain an interconnecting hole, in which a width of an upper part of the interconnecting hole is greater than a width of a lower part of the interconnecting hole.

Abstract: A method of producing a semiconductor memory device includes following operations. A substrate is provided. A stacked structure is formed on the substrate. Capacitor holes arranged at intervals are formed in the stacked structure. Bottom electrode layers are formed in the capacitor holes. A top-layer dielectric layer is removed. A first capacitor dielectric layer is formed on exposed surfaces of a sacrificial layer and surfaces of upper parts of the bottom electrode layers. A first top electrode layer is formed on a surface of the first capacitor dielectric layer. Multiple openings are formed in the first top electrode layer and first capacitor dielectric layer. The sacrificial layer is removed through the openings. A second capacitor dielectric layer is formed. A second top electrode layer is formed on a surface of the second capacitor dielectric layer.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a manufacturing method of a semiconductor structure and a semiconductor structure. The substrate comprises an active region, and the active region is provided with a source region of a first doping type and a drain region of the first doping type; the first dielectric layer is at least partially provided on the substrate and covers a part of the source region and/or a part of the drain region; the second dielectric layer is provided on the substrate, the first dielectric layer is connected to the second dielectric layer, and a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; orthographic projection of the gate structure on the substrate covers orthographic projection of the second dielectric layer and orthographic projection of the first dielectric layer on the substrate.