Abstract: A semiconductor package structure includes: a first base plate; a first semiconductor chip connected to the first base plate; a second semiconductor chip stacking structure including at least one first chip stacking structure and at least one second chip stacking structure; and a plurality of second base plates. The first and second chip stacking structures are arranged side-by-side on the first semiconductor chip in a first direction, a plurality of second conductive bumps are formed on sides of the first and second chip stacking structure that is away from each other in the first direction, the first direction being parallel to a plane where the first base plate is located. A signal line in each second base plate is connected to the second conductive bumps. The second base plates are connected to the first base plate in a direction perpendicular to the plane where the first base plate is located.

Abstract: The disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a storage array located on the substrate and including a plurality of memory cells arranged in an array along a first direction and a second direction, each memory cell including a transistor structure that includes a gate electrode and an active area that includes a first active area and a second active area distributed on opposite sides of the gate electrode along the first direction; a word line extending along the second direction, being continuously and electrically connected with a plurality of gate electrodes in the memory cells arranged at intervals along the second direction; a bit line extending along the first direction and located on outside of each of the memory cells along the second direction.

Abstract: A circuit simulation method includes the following: a key character string corresponding to at least one target power supply node is determined; a node identifier corresponding to the at least one target power supply node is searched out from a first netlist corresponding to the to-be-simulated circuit according to the key character string; and a power supply voltage file corresponding to the at least one target power supply node is generated according to the searched-out node identifier, and the to-be-simulated circuit is simulated according to the power supply voltage file. The circuit simulation method and the device provided by the embodiments of the present disclosure may rapidly generate the power supply voltage file corresponding to the target power supply node, which can not only effectively improve the circuit simulation efficiency, but also ensure the accuracy of a simulation result.

Abstract: A method for determining performance of sequential logic elements includes the following operations. To check a circuit, a performance check file corresponding to each of the sequential logic elements of the circuit is obtained; and the circuit is separately simulated to obtain the simulation result, by using a plurality of simulation waveforms, based on the performance check file corresponding to each of the sequential logic elements. The performance check file may be used to determine, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result.

Abstract: A package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each via exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each first pad is formed by a respective part of the interconnection layer exposed by the corresponding via, N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer is formed on the RDLs and exposes a part area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad.

Abstract: A semiconductor structure and method of manufacturing are disclosed. The semiconductor structure includes: a substrate having an adjacent array area and a peripheral region; a bit line extending along a first direction, a semiconductor channel extending along a second direction and a word line extending along a third direction located on the array area; the ladder structure in the periphery region includes a plurality of steps each is in contact with either the bit line or the word line; a plurality of conductive columns in contact with the top surfaces of the steps and extending along the direction that is the same direction as the other one of the bit line or the word line; and a support frame located between any two adjacent conductive columns and connected to each step of the ladder structure.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, and forming a stacked structure on the substrate; forming a hard mask layer on the stacked structure, where the hard mask layer includes a first etched window, and the first etched window exposes part of a top surface of the stacked structure; forming a photoresist layer, where the photoresist layer covers the first etched window; and trimming the photoresist layer for a plurality of times, after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer, and forming a plurality of steps in the stacked structure along a direction away from the substrate.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, where the substrate includes a first region and a second region, the first region includes a plurality of independent first active regions, adjacent two of the first active regions are isolated by a first trench, and an isolating lamination layer is formed in the first trench; forming a barrier layer covering a top surface of the second region; forming an epitaxial layer covering a top surface of the first active region; and etching off the barrier layer and part of the isolating lamination layer in the first region, where joints of top surfaces of layers in the isolating lamination layer retained in the first region are basically consistent in height.

Abstract: A semiconductor structure includes: a substrate; a stacked structure, contact structures, and storage nodes. The stacked structure is located on the substrate and includes semiconductor layers extending in a first direction and arranged in a spaced manner in a second direction and in a third direction, wherein the first direction and the second direction are directions parallel to a plane where the substrate is located, the first direction is perpendicular to the second direction, and the third direction is a direction perpendicular to the plane where the substrate is located. The contact structures include a first end and a second end in the first direction, wherein the first ends of the contact structures are connected to the semiconductor layers, and a material of the contact structures includes metal silicide. The storage nodes extend in the first direction and are connected to a second end of respective contact structures.

Abstract: The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.

Abstract: A data receiving circuit, data receiving system and storage apparatus are provided. The data receiving circuit includes: a first amplification circuit configured to receive a data signal, first and second reference signals, perform first comparison on the data signal and first reference signal to output a first signal pair and perform second comparison on the data signal and second reference signal to output a second signal pair; a decision equalization enable circuit configured to receive an enable signal and feedback signal and output a control signal where the enable signal has a first level value period, a level value of the control signal varies with that of the feedback signal; and a second amplification circuit configured to receive the first or second signal pair based on the control signal and output first and second output signals.

Abstract: The disclosed semiconductor structure includes: a substrate and a data line on the substrate, the data line extends along a first direction; the first transistor and the second transistor located on the first transistor's side away from the data line; each of the first transistor and the second transistor includes: a semiconductor column, the semiconductor column is located on a part of the top surface of the data line and extends along the third direction; an isolation structure inside the semiconductor column; along the second direction, the thickness of the isolation structure in different regions in the third direction is different, and the isolation structure runs through the semiconductor columns, and two of the first, the second and the third directions intersect each other. This improves the sensitivity of the second transistor to the change in current in the first transistor while reducing the leakage current in the first transistor.

Abstract: A semiconductor package structure includes a first package structure and a second package structure. The first package structure includes a chip stacking structure and a molding compound. A first conductive block is disposed on the chip stacking structure. The molding compound wraps the chip stacking structure and exposes the first conductive block. The second package structure is disposed on the chip stacking structure and electrically connected to the first conductive block. A gap is formed between the first package structure and the second package structure.

Abstract: A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.

Abstract: A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.

Abstract: Disclosed three-dimensional stacked package structure includes: a packaging substrate, having a substrate body, connecting leads, a through-hole penetrating the substrate body, a first pad and a second pad on opposite surfaces of the substrate body. The stacked structure on the first surface of the substrate body includes a second storage block, and a first storage block above the second storage block; the connecting leads include a first lead and a second lead with equal lengths, the first lead is above the package substrate, and one end is electrically connected to the first pad, and the other end is electrically connected to the first storage block. The second lead passes through the through-hole, and one end is electrically connected to the second storage block, the other end is electrically connected to the second pad. The present disclosure reduces the crosstalk between signal lines, thereby reducing signal delay between different storage blocks.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an active pillar including a channel region and a source/drain region arranged on two sides of the channel region; and a gate structure surrounding at least part of the channel region. The channel region includes a peripheral portion and a central portion, the peripheral portion is positioned between the gate structure and the central portion, the source/drain region and the peripheral portion have a first doping type, and the central portion has a second doping type, where the first doping type is one of N-type and P-type, and the second doping type is other one of the N-type and the P-type. At least problems of greater difficulty in turning off existing junctionless field effect transistor and poorer turn-off effect may be solved.

Abstract: A preparation method of the semiconductor structure includes: the substrate including a first area to be etched and a second area to be etched outside the first area to be etched, the etching rate of the first area to be etched and the second area to be etched are different, simultaneously etching the first area to be etched and the second area to be etched at least twice, until an etching depth of one of the first area to be etched and the second area to be etched with a less etching rate is equal to a target etching depth; in at least two etching processes, backfilling a sacrificial material to the first area to be etched and the second area to be etched after a previous etching is completed, removing part of the sacrificial material in a next etching.

Abstract: A method for manufacturing a memory includes: providing a substrate provided with bit lines, each bit line including a plurality of straight line segments connected end to end in sequence, and adjacent straight line segments have an included angle therebetween; forming active pillars and insulating layers on the substrate, each straight line segment of each bit line being electrically connected with at least two active pillars, each insulating layer extending in a first direction and covering the outer peripheral surface of the active pillar; filling a first support layer between adjacent insulating layers; removing part away from the substrate, of each insulating layer to form a filling space; and forming a dielectric layer and a conductive layer between parts exposed in the filling space and close to the substrate, of the active pillars.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure provided by the present disclosure includes: providing a substrate; forming a base pattern on the substrate, where the base pattern includes a plurality of bit lines arranged in parallel, and an isolation structure is disposed between adjacent two of the bit lines; forming a plurality of semiconductor pillars arranged in a direction of the bit line on a surface of each of the bit lines, where the bit line is electrically connected to the semiconductor pillar; forming a gate-all-around structure on a surface of the semiconductor pillar, where the gate-all-around structure includes a first insulating layer, a gate structure layer, and a second insulating layer that are sequentially disposed on a side surface of the semiconductor pillar.