Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Patent number: 12381115Abstract: Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate having a plurality of active area; forming a plurality of bit lines arranged at intervals on the substrate, the plurality of bit lines having a plurality of first mask layers; forming a first dielectric layer on the substrate positioned between adjacent two of the plurality of bit lines; patterning the first dielectric layer, to form a plurality of first notches arranged at intervals on the first dielectric layer; forming a second mask layer on the first dielectric layer, and the second mask layer encircling in each of the plurality of first notches to form a second notch; forming a plurality of contact holes arranged at intervals in the first dielectric layer; and forming a conductive plunger in each of the plurality of contact holes.Type: GrantFiled: August 11, 2021Date of Patent: August 5, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jingwen Lu
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Patent number: 12380940Abstract: A semiconductor device includes: a power down control circuit receiving a power down command signal and a chip selection signal, and generating a power down enable signal and a power down exit signal, here, a logic level of the power down enable signal is converted at a first edge of the power down command signal during a power down stage, and a logic level of the power down exit signal is converted at a second edge of the chip selection signal during a power down exit stage; a power control circuit stopping providing a power voltage according to the power down enable signal during the power down stage, and providing the power voltage according to the power down exit signal during the power down exit stage; and an input buffer circuit transmitting signals during the power down exit stage in response to the power down exit signal.Type: GrantFiled: August 12, 2023Date of Patent: August 5, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yupeng Fan
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Patent number: 12380941Abstract: Embodiments provide a power supply switching circuit, which generates a first control signal jointly by utilizing a first input signal and a first drive signal opposite in phase to a second control signal, and generates the second control signal jointly by utilizing a second input signal and a second drive signal opposite in phase to the first control signal, such that time (i.e., overlap time) required for simultaneously turning on or off a first output subcircuit and a second output subcircuit is greatly reduced or even eliminated, effective output of an output node is implemented, and reliability of a device is improved. Furthermore, compared with eliminating the overlap time by means of delay, eliminating the overlap time by means of the power supply switching circuit is simple and reliable in control logic and is insensitive to process, which further improves the reliability of the device.Type: GrantFiled: June 1, 2023Date of Patent: August 5, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yupeng Fan
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Patent number: 12382696Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a gate structure being provided on a surface of the substrate, and a source region and a drain region being provided in the substrate at two sides of the gate structure, respectively; and a contact located on the substrate, the contact including a first contact located on the substrate and a second contact located on a side of the first contact away from the substrate, in which an area of a bottom surface of the first contact is greater than an area of a top surface of the second contact.Type: GrantFiled: September 28, 2022Date of Patent: August 5, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jifeng Tang
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Patent number: 12380939Abstract: A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.Type: GrantFiled: August 9, 2023Date of Patent: August 5, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Lu Liu
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Patent number: 12374382Abstract: A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock receiving circuit, configured to receive an initial clock signal and perform frequency division processing on the initial clock signal to obtain a first clock signal; a sampling and logic circuit, configured to perform two-stage sampling processing and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a chip select clock signal, where the chip select clock signal includes two pulses, and the width of each pulse is a preset clock cycle; and a decoding circuit, configured to perform decoding processing and sampling processing on the to-be-processed command signal according to the to-be-processed chip select signal and the chip select clock signal to obtain a target command signal.Type: GrantFiled: September 28, 2022Date of Patent: July 29, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zequn Huang
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Patent number: 12374389Abstract: The present disclosure provides a memory bank and a memory. The memory bank includes: multiple memory arrays arranged along a first direction, each of the memory arrays being divided into at least two array units along a second direction, and the first direction and the second direction being perpendicular to each other; multiple read-write control circuits, the read-write control circuits being provided between adjacent two of the memory arrays; and multiple data signal lines configured to electrically connect the read-write control circuits and the array units; wherein, different array units of each of the memory arrays are electrically connected to different read-write control circuits through different data signal lines.Type: GrantFiled: January 13, 2023Date of Patent: July 29, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Weibing Shang, Hongwen Li
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Patent number: 12372571Abstract: A method for detecting a layout of an integrated circuit includes: a finger structure is determined in the layout, the finger structure including at least one upper connection source-drain terminal and at least one upper connected via, the at least one upper connected source-drain terminal being electrically connected to an upper metal line through the at least one upper connected via; a number of the at least one upper connected source-drain terminal and a number of the at least one upper connected via are calculated; and for the finger structure, in response to the number of the at least one upper connected source-drain terminal being greater than the number of the at least one upper connected via, it is determined that the finger structure is an unqualified finger structure.Type: GrantFiled: June 8, 2022Date of Patent: July 29, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Miaomiao Chen
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Patent number: 12374550Abstract: A photomask assembly includes: a first photomask for forming a first patterned structure, the first patterned structure having a first patterned opening which includes a plurality of strip-shaped patterns, a distance between the strip-shaped patterns at the two sides of a boundary between the first region and the second region being greater than a distance between other every two neighboring strip-shaped patterns when the center of the first photomask coincides with the center of the substrate; and a second photomask for forming a second patterned region which covers a first patterned opening of a second region, a distance between an opening edge of the second patterned structure and the neighboring strip-shaped pattern being greater than a first preset distance when the center of the second photomask and the center of the first photomask coincide with the center of the substrate.Type: GrantFiled: September 30, 2021Date of Patent: July 29, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Fufang Chao, Junjun Zhang, Zhimin Wu
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Patent number: 12374384Abstract: A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.Type: GrantFiled: August 11, 2023Date of Patent: July 29, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zequn Huang
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Patent number: 12374585Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate having a connection hole thereon, annular protrusions and annular grooves alternately arranged along a direction parallel to a center line of the connection hole being provided on a hole wall of the connection hole; filling a barrier block in each of the annular grooves; removing the annular protrusions along a direction perpendicular to the hole wall of the connection hole; removing the barrier blocks; and forming a connection layer in the connection hole. After the annular protrusions are removed, roughness of the hole wall of the connection hole is reduced, such that a conductive seed layer is prevented from being broken, thereby avoiding generation of voids in the connection layer, and improving performance of the semiconductor structure.Type: GrantFiled: September 27, 2022Date of Patent: July 29, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chih-Wei Chang
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Patent number: 12368051Abstract: A method of manufacturing a semiconductor test sample includes: providing a product to be analyzed, the product comprises a conductive interconnection layer and a semiconductor doped region located below the conductive interconnection layer; selectively removing a conductive material from the conductive interconnection layer, replacing the conductive material with a non-conductive material and replacing the conductive interconnection layer with an insulating sacrificial layer; and taking the product including both the insulating sacrificial layer and the semiconductor doped region as a semiconductor test sample.Type: GrantFiled: July 22, 2021Date of Patent: July 22, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Rui Ding
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Patent number: 12362025Abstract: An anti-fuse address decoding circuit includes: a pre-decoding circuit, configured to decode a programming address of an anti-fuse memory array and output a programming address pre-decoded signal; a level shift circuit, coupled to the pre-decoding circuit, and configured to boost the programming address pre-decoded signal and output a boosted signal; and a programming address decoding circuit, configured to receive the boosted signal, decode the boosted signal and output a programming address signal.Type: GrantFiled: February 9, 2023Date of Patent: July 15, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Rumin Ji
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Patent number: 12363889Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; pre-processing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.Type: GrantFiled: August 4, 2022Date of Patent: July 15, 2025Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGYInventors: Deyuan Xiao, Yong Yu, Guangsu Shao
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Patent number: 12364167Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; forming a first shielding layer on the substrate; forming a first electrode penetrating the first shielding layer; forming a storage structure on the first electrode; forming a second shielding layer on the top surface and sidewalls of the storage structure, wherein the first shielding layer and the second shielding layer combine into one integrated shielding layer; and forming a second electrode which penetrates the shielding layer and electrically connects to the storage structure.Type: GrantFiled: March 9, 2021Date of Patent: July 15, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: YuLei Wu, Baolei Wu, Xiaoguang Wang, Er-Xuan Ping
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Patent number: 12363951Abstract: Embodiments provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, having a first region and a second region; a first gate structure positioned in the first region and a second gate structure positioned in the second region, the first gate structure being a high dielectric constant gate including a first gate electrode layer and a high dielectric constant layer, and the second gate structure including a second gate electrode layer and an oxide insulating layer; a spacer and an interlayer dielectric layer, positioned on the first gate structure and the second gate structure, the spacer and the interlayer dielectric layer covering a part of the second gate structure, the substrate, and the first gate structure; and a second contact plug, penetrating through the spacer and the interlayer dielectric layer and being in contact with the substrate.Type: GrantFiled: June 21, 2022Date of Patent: July 15, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Yutong Shen, Jifeng Tang
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Patent number: 12362001Abstract: The present disclosure provides a voltage generating circuit and a memory. The voltage generating circuit includes: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, where the power supply node is connected to a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage and generate and output a control signal; and a compensation module configured to receive a power voltage, a flag signal and the control signal, be turned on in response to the flag signal, and configured to provide a second output voltage to the power supply node in response to a voltage value of the control signal, such that a voltage of the power supply node is recovered to the first output voltage.Type: GrantFiled: August 3, 2023Date of Patent: July 15, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jianyong Qin
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Patent number: 12354971Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure at least includes two photolithography layers which are arranged in sequence and at least one blocking layer. Each photolithography layer includes a functional pattern and an overlay mark, and the photolithography layers include a first photolithography layer and a second photolithography layer. The first photolithography layer includes a first functional pattern and a first overlay mark, and the second photolithography layer includes a second functional pattern and a second overlay mark; and at least one blocking layer. The blocking layer is located between the first functional pattern and the second functional pattern, and a vertical distance between the first functional pattern and the second functional pattern is greater than a vertical distance between the first and second overlay marks, in a stacking direction of the photolithography layers.Type: GrantFiled: June 10, 2022Date of Patent: July 8, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shaowen Qiu
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Patent number: 12353124Abstract: Embodiments of the present disclosure disclose a lithography method, a lithography apparatus, and a computer storage medium. The method includes: determining an exposure intensity of a mask aligner; determining a target preset interval corresponding to the mask aligner according to the exposure intensity; determining, according to the target preset interval, at least one target wafer for which at least one exposure dose is a target exposure dose, the target preset interval has a corresponding relationship with the target exposure dose; and performing lithography process on the at least one target wafer by using the mask aligner.Type: GrantFiled: June 28, 2022Date of Patent: July 8, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Heng Wang
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Patent number: 12354706Abstract: A control apparatus includes: a receiving circuit, configured to receive a read clock signal from the memory, and output the read clock signal; a clock circuit, configured to generate a first internal clock signal; a selection circuit, configured to receive the read clock signal and the first internal clock signal, and output one of the read clock signal and the first internal clock signal as a target read clock signal; and a latch circuit, configured to receive the target read clock signal and a read data signal sent by the memory, and perform latch processing on the read data signal by using the target read clock signal.Type: GrantFiled: January 14, 2023Date of Patent: July 8, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Jingwei Cheng