Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Patent number: 12334393
    Abstract: The disclosed method provides a solution to the gate-induced drain leakage (GIDL) current in a semiconductor structure. The method includes forming a first trench with a first initial doped region at its bottom, oxidizing the first trench, forming a first oxide layer on the sidewalls of the first trench, and forming a second oxide layer at the bottom of the first trench. The first oxide layer's thickness is greater than the second oxide layer's thickness. The doping element of the first initial doped region prolongs the reduction rate, so that the oxidation rate of the first initial doped region is lower than the oxidation rate of the substrate, thereby forming the first oxide layer. The GIDL of the semiconductor structure can be reduced, the turn-on sensitivity of the semiconductor structure can be improved, and the yield of the semiconductor structure can be increased.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 17, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jian Yang
  • Patent number: 12336172
    Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure and a fabricating method thereof. The semiconductor structure includes: a substrate (100), and a gate oxide layer (110) on a surface of the substrate (100); a gate stack layer (120) positioned on a surface of the gate oxide layer (110); a spacer(130) at least covering a first sidewall of the gate stack layer (120); a contact structure (140) at least positioned on the surface of the substrate (100); and a dielectric layer (150) at least positioned between the contact structure (140) and a second sidewall of the gate stack layer (120). The first sidewall and the second sidewall are arranged opposite to each other, and a thickness of the dielectric layer (150) is less than a thickness of the spacer(130). A breakdown difficulty of a fuse structure may be reduced at least.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: June 17, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Patent number: 12327610
    Abstract: Embodiments provide a data receiving circuit. The data receiving circuit includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit is configured to receive a data signal, a first reference signal and a second reference signal, perform a first comparison between the data signal and the first reference signal and output a first signal pair, and perform a second comparison between the data signal and the second reference signal and output a second signal pair. The second amplifier circuit is configured to select to receive the first signal pair or the second signal pair as input signal pairs based on a feedback signal, amplify a voltage difference between the input signal pairs, and output a first output signal and a second output signal, wherein the feedback signal is obtained based on previously received data.
    Type: Grant
    Filed: January 14, 2023
    Date of Patent: June 10, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Feng Lin
  • Patent number: 12327740
    Abstract: A method for adjusting a chip mounting position, an apparatus, a medium, and an electronic device are provided. The adjustment method includes: obtaining offsets of actual mounting positions of individual chips in a first group of chips; obtaining an average offset for the actual mounting positions of the individual chips in the first group of chips according to the offsets of the actual mounting positions of the individual chips in the first group of chips; and adjusting the chip mounting position according to the average offset for the actual mounting positions of the individual chips in the first group of chips.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: June 10, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Hailin Wang
  • Patent number: 12322654
    Abstract: A method for forming the semiconductor structure includes: a wafer in which a semiconductor device is formed is provided; a blind hole is formed in the wafer; a first metal material is deposited in the blind hole to form a through silicon via; and a first metal material deposited on a surface of the wafer is removed, and the surface of the wafer is planarized.
    Type: Grant
    Filed: August 23, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yuanhao Gao
  • Patent number: 12324139
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaojie Li
  • Patent number: 12321157
    Abstract: A state monitoring method, a state monitoring apparatus and a state monitoring system for a developing device are provided. After image information is obtained through the acquired video information of the developing device, it is determined by an analysis unit whether the image information includes nozzle anomaly information, and alarm information is issued after the nozzle anomaly information is determined. Moreover, similarity between the image information that does not include the nozzle anomaly information and second preset nozzle anomaly information is compared, and the nozzle information is stored in the analysis unit in a case that the similarity between the image information and the second preset nozzle anomaly information is greater than a first threshold.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaojun Liu
  • Patent number: 12322589
    Abstract: Embodiments of the disclosure provide a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate including a plurality of active areas and first isolation structures arranged at intervals along a first direction; gate structures located in the active areas and the first isolation structures. Top surfaces of the active areas extend beyond top surfaces of the gate structures; second isolation structures with a preset height located on surfaces of the gate structures, and the top surfaces of the second isolation structures are flush with the top surfaces of the active areas.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiang Liu
  • Patent number: 12322612
    Abstract: The present disclosure provides a heating device and heating method for a semiconductor thermal process. The heating device includes: a first heating portion, on which a wafer to-be-heated is placed; a second heating portion, where the first heating portion and the second heating portion are arranged in parallel, and the second heating portion is configured to heat the first heating portion; and an adjustment portion, configured to adjust a vertical distance between the first heating portion and the second heating portion.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wanzheng Chen, Le Wang
  • Patent number: 12322671
    Abstract: A guard ring structure includes: a bottom metal layer; a protection structure located on the bottom metal layer, wherein the protection structure includes an insertion portion, an interconnection portion, and a metal layer stacked in sequence from bottom to top, and the insertion portion is inserted into the nearest underlining metal layer under the interconnection.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Hua Yan, Hsin-Pin Huang
  • Patent number: 12324141
    Abstract: A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Juanjuan Huang, Yi Jiang, Weiping Bai, Deyuan Xiao
  • Patent number: 12323161
    Abstract: A data error correction circuit includes: a data error correction circuit, configured to receive first data and a first check code corresponding to the first data, perform error correction on the first data according to the first check code to generate second data, and output the second data; and a check code generation circuit, configured to receive the first data and the first check code, generate a second check code according to the first data and the first check code, and output the second check code.
    Type: Grant
    Filed: January 7, 2023
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kangling Ji
  • Patent number: 12324148
    Abstract: The embodiments of the present application provide a semiconductor structure manufacturing method for forming a semiconductor structure.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Patent number: 12324359
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a substrate; forming bottom contact structures in the substrate; forming a storage unit on each of the bottom contact structures; and forming shielding structures that each wrap around one of the storage units, wherein the shielding structures each include multiple dielectric layers and shielding layers arranged alternately.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yulei Wu
  • Patent number: 12324212
    Abstract: Provided are a semiconductor structure and method for preparing same. The semiconductor structure includes a gate, a source or a drain being provided in the substrate at either side of the gate; a dielectric layer; a contact structure; a first electrical connection part and a second electrical connection part arranged at intervals. The second electrical connection part is in contact with a partial top surface of the contact structure. The first electrical connection part includes a first barrier layer and a first conductive layer which are stacked. In a direction from the source to the drain, a distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and a distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tieh-Chiang Wu, Lingxin Zhu
  • Patent number: 12324147
    Abstract: A method for forming a semiconductor structure includes: a substrate is provided, in which active areas arranged in a matrix and isolation structures for isolating active areas from each other are formed in substrate, a first direction is a column direction of matrix and a second direction is a row direction of matrix; a conductive layer is formed on substrate; at least conductive layer is etched to form a plurality of bit line grooves extending along first direction and arranged along second direction and a plurality of conductive lines extending along first direction and arranged along second direction; a bit line structure is formed in each bit line groove, in which a gap is formed between bit line structure and each of two sides of a respective one of bit line grooves; and conductive lines are etched along second direction to form conductive pillars serving as storage node contact structures.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 3, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jinghao Wang, Junbo Pan
  • Patent number: 12315555
    Abstract: An amplification circuit includes a sense amplification circuit, including a read node SABL, a complementary read node SABLB, a first node PCS, and a second node NCS; an isolation circuit, coupled to the SABL, the SABLB, a hit line BL, and a complementary hit line BLB, configured to: in a sense amplification stage, couple the SABL to the BL and couple the BLB to the SABLB; an offset cancellation circuit, coupled to the BL, the BLB, the SABL, and the SABLB, configured to: in an offset cancellation stage, couple the BL to the SABLB and couple the BLB to the SABL; and a first power supply circuit, coupled to the PCS, and configured to: acquire memory temperature information, and in the offset cancellation stage, adjust, according to the memory temperature information, a magnitude of a power supply voltage provided to the PCS.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: May 27, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Hongwen Li
  • Patent number: 12317472
    Abstract: A method for manufacturing a semiconductor device includes the following operations. A substrate is provided. Bit lines extending in a first direction are formed on the substrate. A first dielectric layer is formed on the bit lines. The first dielectric layer is etched from top to bottom to form channel holes in the first dielectric layer, in which the channel holes expose the bit lines. A channel layer is formed in each channel hole, in which the channel layer includes a first source/drain area, a channel area and a second source/drain area which are arranged from bottom to top, the first source/drain area is electrically connected to a respective one bit line. Word lines extending in a second direction are formed in the first dielectric layer.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: May 27, 2025
    Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Deyuan Xiao, Yong Yu, Guangsu Shao
  • Patent number: 12311500
    Abstract: A polishing liquid supply system, polishing apparatus, exhausting method and polishing method are provided. The system includes a polishing liquid filter; a sensor for detecting whether there are bubbles in the polishing liquid filter; a controller which is connected to the polishing machine and the sensor, and configured to send an exhaust signal when the polishing machine is in an idle state and the sensor detects that there are bubbles in the polishing liquid filter; and an exhaust unit which includes an exhaust pipeline and a control valve, wherein the exhaust pipeline is in communication with the inside of the polishing liquid filter, and the control valve is arranged on the exhaust pipeline and is connected to the controller for opening after receiving the exhaust signal so as to exhaust the bubbles.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: May 27, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Peng Zhang, Fan-Wei Liao
  • Patent number: 12315795
    Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure includes: providing a base, the base including a substrate and a first dielectric layer on the substrate; forming a through silicon via in the base, the through silicon via penetrating through the first dielectric layer, extending into the substrate, and having a depth less than a thickness of the base; forming an electrically conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounding the electrically conductive structure, exposing a sidewall of the electrically conductive structure and a part of the substrate, and having a stepwise sidewall; and forming a thermally conductive structure in the filling hole.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: May 27, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Luguang Wang, Xiaoling Wang