Abstract: The embodiments of the present disclosure provide a polishing head management system and method. The polishing head management system includes: a storage device, a pick-and-place device and a data acquisition device, where the storage device is used to store polishing heads; the pick-and-place device is used to pick a polishing head or place a polishing head into the storage device; the data acquisition device is connected with the storage device and the pick-and-place device, and is used to record at least one management cycle of the polishing head.

Abstract: The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and in particular to a method of manufacturing a semiconductor structure, a semiconductor structure and a memory. The method of manufacturing a semiconductor structure includes: forming a first semiconductor layer on a substrate, the first semiconductor layer including a first trench region and a to-be-doped region on two opposite sides of the first trench region; forming a word line, the word line surrounding a sidewall surface of a part of the first semiconductor layer in the first trench region, and at least a part of a projection of a part of the first semiconductor layer in the to-be-doped region on a surface of the substrate coinciding with a projection of the word line on the surface of the substrate; forming a doping body portion, the doping body portion including first dopant ions.

Abstract: A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.

Abstract: The present disclosure provides a method of forming a photoresist pattern and a projection exposure apparatus. The forming method includes: providing a photoresist layer, and disposing the photoresist layer under a projection objective, wherein a light refracting plate is located between the photoresist layer and the projection objective; and performing an exposure processing on the photoresist layer through the projection objective and the light refracting plate, and forming an exposure image in the photoresist layer, wherein the light refracting plate is configured to reduce a wavelength of optical waves entering the photoresist layer.

Abstract: Embodiments of the present disclosure disclose a semiconductor base plate and a semiconductor device. An array region includes a primary memory cell. A peripheral region includes an antifuse memory cell. The antifuse memory cell and the primary memory cell are formed by a same process.

Abstract: A semiconductor structure and a forming method thereof are provided. The method for forming a semiconductor structure includes providing a base including a semiconductor substrate and a well region located on a surface of the semiconductor substrate, in which the well region includes a plurality of active pillar columns arranged at intervals along a first direction, and each of the active pillar columns includes a plurality of active pillars arranged at intervals along a second direction, in which the first direction is perpendicular to the second direction; forming a plurality of bit line trenches by etching at least the well region and a partial thickness of the semiconductor substrate at bottoms of the active pillars; and forming buried bit lines in the bit line trenches.

Abstract: A test circuit includes first integration circuit configured to receive first test signal and integrate first test signal to output first integrated signal; second integration circuit configured to receive second test signal and integrate second test signal to output second integrated signal, where first test signal and second test signal are signals inverted with respect to each other, value of first integrated signal is product of duty cycle of first test signal and a voltage amplitude of power supply, and value of second integrated signal is product of duty cycle of second test signal and voltage amplitude of power supply; and comparison circuit connected to first and second integration circuits. The comparison circuit is configured to output high-level signal in response to first integrated signal being greater than second integrated signal, and output low-level signal in response to second integrated signal being greater than first integrated signal.

Abstract: A sense amplifier circuit architecture includes a first NMOS layout, a second NMOS layout, a first PMOS layout, a second PMOS layout, a first processing structure layout and a second processing structure layout. The first NMOS layout includes first N-type active layers and first gate layers discretely arranged on the first N-type active layers. The second NMOS layout includes second N-type active layers and second gate layers discretely arranged on the second N-type active layers. The first PMOS layout includes first P-type active layers and third gate layers discretely arranged on the first P-type active layers. The second PMOS layout includes second P-type active layers and fourth gate layers discretely arranged on the second P-type active layers. The first processing structure layout includes first active layers and a first isolation gate. The second processing structure layout includes second active layers and a second isolation gate.

Abstract: An anti-fuse unit structure includes a substrate, an anti-fuse device, and a select transistor. The anti-fuse device is formed in the substrate and comprises a first gate structure, a first source doped region, and a first drain doped region, wherein the first gate structure is electrically connected to the first drain doped region. The select transistor is formed in the substrate and matched with the anti-fuse device, and comprises a second gate structure, a second source doped region and a second drain doped region, wherein the second drain doped region is electrically connected to the first source doped region.

Abstract: Provided are a data transmission circuit, a data transmission method, and a storage device. The data transmission circuit includes a controllable delay module and a mode register data processing unit. The controllable delay module is configured to generate a delayed read command in response to a mode register read command. The mode register data processing unit is configured to read setting parameters from a mode register in response to the mode register read command, and to output the setting parameters in response to the delayed read command. Here, a time difference between a start moment of outputting of the setting parameters and a moment when the controllable delay module receives the mode register read command is a first preset threshold.

Abstract: The present disclosure provides a calibration circuit, a memory, and a calibration method. The calibration circuit includes: a calibration resistance module, wherein an output voltage of the calibration resistance module varies with a first parameter, and the first parameter includes at least one of a fabrication process of the calibration circuit, a power supply voltage of the calibration circuit, or an operating temperature of the calibration circuit; a reference voltage generation module, configured to receive a first comparison signal, to generate a corresponding reference voltage; and a comparison module, coupled to the calibration resistance module and the reference voltage generation module, and configured to compare the output voltage with the reference voltage and generate the first comparison signal.

Abstract: Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate, with word lines arranged at intervals in the substrate, and trenches between adjacent word lines; a bit line contact layer, wherein the bottom surface of the bit line contact layer is in contact with the bottom surface of the trench, and the bit line contact layer has a non-planar contact portion in the direction away from the bottom surface of the trench; the conductive layer is in contact with the non-planar contact portion of the bit line contact layer. The embodiments of the present application are beneficial in reducing the resistance of the bit line itself including the bit line contact layer and the conductive layer, thereby helping to improve the electrical performance of the semiconductor structure.

Abstract: The present disclosure provides a manufacturing method of a semiconductor device, including: providing a substrate; forming a film stack structure on the substrate, a top of the film stack structure being a cover layer; forming a mask structure on the cover layer, the mask structure including a mask layer and a pattern transfer layer sequentially stacked from top to bottom; performing a first etching on the mask structure to form first blind holes, the first blind holes running through the mask structure and terminating in the cover layer; and performing a second etching on the mask structure, and removing the mask layer, to flatten a top surface of the pattern transfer layer and trim bottoms of the first blind holes.

Abstract: A method for manufacturing a semiconductor structure, including: providing a base; forming a Through Silicon Via (TSV) in the base, with a depth of the TSV being less than a thickness of the base; and forming a liner layer on a sidewall and the bottom of the TSV, and forming a conductive layer in the TSV, the liner layer including a polish-stop layer.

Abstract: Embodiments of this invention provide a voltage output test circuit, a voltage divider output circuit, and a memory. The voltage output test circuit includes: a first voltage divider unit, including a first terminal and a second terminal, where the first terminal of the first voltage divider unit is connected to a test power supply, and the second terminal of the first voltage divider unit is connected to an output terminal; a second voltage divider unit, including a first terminal and a second terminal, where the first terminal of the second voltage divider unit is connected to a ground, and the second terminal of the second voltage divider unit is electrically connected to the output terminal; and a third voltage divider unit, configured to adjust a resistance between the output terminal and the ground.

Abstract: A method for preparing a semiconductor device is provided. The method for preparing the semiconductor device includes: providing a substrate, and forming a first dielectric layer on one side of the substrate, where the substrate includes an array area and a peripheral area arranged outside of the array area; forming an initial mask pattern on one side of the first dielectric layer away from the substrate; performing at least two patterning processes on the initial mask pattern, to form a first mask pattern in the array area and to form a second mask pattern in the peripheral area. The first mask pattern has a first height, the second mask pattern has a second height, and the second height is greater than the first height. Both of the array area and the peripheral area are exposed by using each of the at least two patterning processes.

Abstract: A semiconductor integrated circuit design method and apparatus, and relates to the technical field of semiconductors are provided. The semiconductor integrated circuit design method includes: determining, based on an original layout, an original length of an end of a gate structure extending out of an active region in which the gate structure is located; redetermining, based on a preset rule and the original length, a correction length of the end of the gate structure extending out of the active region in which the gate structure is located; and integrating the original layout and the correction lengths, and forming an updated layout.

Abstract: A system for controlling the non-product wafer includes the following: a monitoring module, configured to monitor the state of the non-product wafer; a statistics module, configured to obtain usage information of the non-product wafer; and a control module, configured to receive a production instruction and control the non-product wafer according to the state and the usage information of the non-product wafer. The disclosure implements the purpose of automatic control and management of the non-product wafer.

Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a base; forming a lower dielectric layer; forming a first lower conductive pillar located in an array area, a second lower conductive pillar located in a peripheral area and a third lower conductive pillar located in a core area; forming an upper dielectric layer that exposes top surfaces of the first lower conductive pillar, the second lower conductive pillar and the third lower conductive pillar; and forming a first upper conductive pillar, a second upper conductive pillar and a third upper conductive pillar that are located within the upper dielectric layer; in which the third upper conductive pillar and the third lower conductive pillar constitute a third conductive pillar, and a top surface area of the third lower conductive pillar is larger than a top surface area of the third upper conductive pillar.