Abstract: A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes a master chip and a plurality of slave chips. The master chip and the slave chips are each provided with a first transmission terminal and a second transmission terminal, where the first transmission terminals are connected to each other, and the second transmission terminals are connected to each other; and a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in the slave chip, the address transmitter is configured to send an address signal; a current slave chip sends the ZQ flag signal after completing the calibration; and the address transmitter is configured to send a next address signal.

Abstract: Embodiments provide a semiconductor structure and a fabricating method. The method includes: providing a substrate, where a plurality of active areas arranged at intervals are provided in the substrate, and the substrate is covered with an insulating layer and a barrier layer stacked sequentially; forming, in the barrier layer, a plurality of first trenches arranged at intervals and extending along a first direction and penetrating through the barrier layer; forming a filling layer in the first trenches, and forming a first mask layer on the barrier layer and the filling layer; forming, in the first mask layer, a plurality of second trenches arranged at intervals and extending along a second direction and exposing the filling layer; and removing the filling layer exposed in the second trench and the insulating layer corresponding to the filling layer to form contact holes.

Abstract: A semiconductor structure includes a substrate, a gate structure, a cover layer and a first sacrificial structure. The substrate includes discrete semiconductor channels arranged at a top of the substrate. The gate structure is disposed in a middle region of a semiconductor channel, and includes a ring structure and a bridge structure. The ring structure encircles the semiconductor channel, and the bridge structure penetrates through the semiconductor channel and extends to an inner wall of the ring structure along a penetrating direction. The cover layer is located between adjacent semiconductor channels, and includes a first communication hole. The first sacrificial structure is located on the cover layer, and includes a second communication hole. An inner sidewall of the second communication hole has an irregular shape.

Abstract: Embodiments of the present application provide a memory array circuit, a memory array layout and a verification method. The memory array circuit includes: M word lines (WLs); M WL break nodes, each being configured to separate a corresponding one of the WLs into a first WL pin and a second WL pin; N bit lines (BLs); and N BL break nodes, each being configured to separate a corresponding one of the BLs into a first BL pin and a second BL pin, wherein the M and the N each are a positive even number.

Abstract: A semiconductor structure includes: a Magnetic Random Access Memory (MRAM) cell, including a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack and a top electrode; an insulating layer covering a sidewall partially and a top surface of the MRAM cell; a first dielectric layer, a stop layer and a second dielectric layer sequentially stacked on the insulating layer; and a top electrode contact hole penetrating through the second dielectric layer, the stop layer, the first dielectric layer and the insulating layer, and extending to the top electrode, where the top electrode contact hole includes a first portion and a second portion connected with each other in the stop layer, and a radial width of the second portion in contact with the top electrode is gradually decreased with an increase in a depth of the top electrode contact hole. Method for manufacturing the structure and semiconductor memory are also provided.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming active pillars arranged at intervals on the substrate, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially along a first direction; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a word line structure on a sidewall of the gate oxide layer, the word line structure includes a first word line structure and a second word line structure that are made of different materials, and the first word line structure is connected to the sidewall of the gate oxide layer, and partially covers the second word line structure.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.

Abstract: The present disclosure provides a semiconductor structure, including a stacked structure, wherein the stacked structure includes a plurality of stacked semiconductor dies, and each of the semiconductor dies includes: a first base; a channel provided on the first base; and at least one first auxiliary through electrode and a plurality of connection through electrodes running through the first base, wherein the at least one first auxiliary through electrode is surrounded by the plurality of connection through electrodes, wherein connection through electrodes of adjacent ones of the semiconductor dies are connected through a first electrical connection structure to form a plurality of mutually isolated transmission paths, and each of the transmission paths is connected to at least one channel through at least one connection through electrode thereon.

Abstract: The present application discloses a material handling system and a monitoring system and a monitoring method for particles in a traveling area of overhead hoist transfers, wherein the monitoring system for particles in the overhead hoist transfer traveling area comprises gas sampling modules, a particle counter and a monitoring device. The gas sampling module is configured to obtain the gas to be tested around traveling wheels of each overhead hoist transfer (OHT). The particle counter is configured to test the gas to be tested for the size and number of particles in the gas to be tested. The monitoring device is electrically connected to the particle counter, and is configured to acquire the size and number of the particles tested and alarm when determining that the content of particles does not meet a preset standard.

Abstract: A preparation method for a semiconductor structure and a semiconductor structure are provided. Herein, the preparation method comprises: providing a structure to be processed, wherein the structure to be processed comprises a substrate, and an etching target layer, a bottom mask layer and a first mask layer stacked on the substrate; patterning the first mask layer to form a first pattern, the first pattern exposing parts of the bottom mask layer; forming spacers with vertical sidewall morphology on sidewalls of the first mask layer; removing the first mask layer; filling a gap between the spacers with a filling layer, in which a material of the spacers to a material of the filling layer has a high etching selectivity ratio; and removing the spacers.

Abstract: Embodiments of the present disclosure provide an apparatus match detection method, a detection system, a prewarning method and a prewarning system, the apparatus match detection method includes: providing a to-be-detected wafer, a first detection apparatus, and a second detection apparatus; measuring by the first detection apparatus a critical dimension of the first detection area to acquire a first detection result; measuring by the second detection apparatus a critical dimension of the third detection area to acquire a third detection result; measuring by the first detection apparatus a critical dimension of the second detection area to acquire a second detection result; acquiring a measurement difference between the first detection apparatus and the second detection apparatus based on the first detection result, the second detection result, and the third detection result; and acquiring a degree of deviation between the second detection apparatus and the first detection apparatus based on the measurement di

Abstract: Embodiments of the present disclosure provide a method of manufacturing a magnetic random access memory (MRAM) and a MRAM. The method includes: preparing a bottom electrode through hole, a bottom electrode, a magnetic tunnel junction (MTJ), a top electrode, and an insulating layer sequentially on a semiconductor substrate; forming a first interlayer dielectric layer on the insulating layer; forming an etching stop layer on the first interlayer dielectric layer; forming a second interlayer dielectric layer on the etching stop layer; etching a part of the second interlayer dielectric layer above the top electrode to the etching stop layer, and forming a first trench; performing a self-alignment implantation inclined on a part of the first interlayer dielectric layer corresponding to a bottom of the first trench; continuously etching through the first trench to a top end surface of the top electrode, and forming a second trench.

Abstract: A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.

Abstract: A method for detecting wafer cleaning anomalies includes: capturing a wafer cleaning video in real time through each of a plurality of cameras of cleaning machines, each camera corresponds to a respective cleaning chamber of one of the cleaning machines, and each cleaning chamber contains a nozzle; performing image processing on each frame of image contained in the wafer cleaning video to obtain characteristics of contact between a cleaning water column dispensed from the nozzle and a wafer in the image, and determining through the characteristics of contact whether the nozzle has an anomaly; and when a target nozzle having the anomaly is detected, determining anomaly positioning information of the target nozzle, and performing anomaly early-warning by using the anomaly positioning information.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes providing a substrate having trenches, regions other than the trenches in the substrate form a plurality of active regions at intervals; forming a first isolation layer and a second isolation layer, a top surface of the first isolation layer is lower than a top surface of the second isolation layer, a groove is formed between the second isolation layer and the active region; forming a barrier layer in the groove, an etching rate of the barrier layer is lower than an etching rate of the first isolation layer; and forming a third isolation layer in an intermediate trench, the intermediate trench is filled with the third isolation layer, and the first isolation layer, the second isolation layer, the third isolation layer, and the barrier layer form an isolation structure.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a forming method of a semiconductor structure and a semiconductor structure. The forming method of a semiconductor structure includes: placing a target structure in a reaction chamber; forming a first oxide layer on the target structure, where the first oxide layer has a first thickness; and forming a second oxide layer under the first oxide layer, where the second oxide layer has a second thickness, and the first thickness is less than the second thickness.

Abstract: The invention provides a semiconductor structure and a manufacturing method making the semiconductor structure. The method includes: providing a substrate; forming semiconductor pillars on the substrate; forming gate electrodes on the middle sidewalls of the semiconductor pillars; and performing dopant implantation to form source and drain regions. Since the gate-all-around (GAA) gates surrounding the semiconductor pillars are formed first, and the source region and the drain region are formed later by doping implantation, the precise position of the doping implantation can be ensured, thereby improving the fabrication accuracy of the semiconductor structure and improving the performance of the semiconductor structure.

Abstract: The present disclosure provides a semiconductor structure, including: a plurality of metal layers and a substrate, wherein the plurality of metal layers include a first metal layer, a second metal layer, and a third metal layer; a plurality of virtual metal blocks and at least one signal line are disposed on the metal layers; the virtual metal blocks on the metal layers are staggered in a direction perpendicular to the substrate; a second distance between a projection of a target signal line on the substrate and a projection of a second virtual metal block on the substrate is greater than a first distance between the projection of the target signal line on the substrate and a projection of a first virtual metal block on the substrate; the target signal line is located on the first metal layer.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a conductive layer having a recessed side surface facing toward the conductive plug. Compared with a traditional gate structure, in the solutions of the present disclosure, a distance between the conductive layer having the recessed side surface and the conductive plug is increased, thereby reducing a parasitic capacitance between the gate structure and the conductive plug, such that capacitances between a gate and the source/drain region are reduced, and device characteristics are improved.