Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.

Abstract: A delay circuit includes a self-shielding circuit and a delay. The self-shielding circuit is configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N?1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases. The delay is electrically connected to the self-shielding circuit and is configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal. Thus, the accuracy of signal processing can be improved.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.

Abstract: Provided is a preparation method of a semiconductor device, including the following steps: providing a substrate and forming a mask layer with a plurality of first windows on the substrate; forming a dielectric layer, the dielectric layer at least covering sidewalls of the first windows; forming a first photoresist material layer, the first photoresist material layer covering the dielectric layer and the mask layer and filling the first windows; patterning the first photoresist material layer to form a patterned first photoresist layer which exposes a top surface of the dielectric layer; by using the first photoresist layer and the mask layer as masks, removing the dielectric layer to form second windows; and removing part of the substrate along the second windows to form a patterned substrate.

Abstract: The present application relates to the technical field of semiconductors, and in particular, to a wafer scheduling method and a wafer scheduling apparatus for an etching equipment. The wafer scheduling method includes: obtaining a wafer processing request, where the wafer processing request includes at least process information of wafers and an equipment processing parameter of the etching equipment; responding to the wafer processing request, and determining a wafer scheduling parameter corresponding to the process information and the equipment processing parameter, based on the process information, the equipment processing parameter, and a preset wafer scheduling policy, where the wafer scheduling parameter is used to determine a transfer time for transferring the wafers to the etching equipment for processing; and performing wafer scheduling processing on the wafers by using the wafer scheduling parameter. In this way, the wafer processing productivity of the etching equipment can be improved.

Abstract: The present disclosure provides a memory device and a ZQ calibration method. The memory device includes: two calibration resistor interfaces connected to a same ZQ calibration resistor; a first master chip, a plurality of first slave chips cascaded together, a second master chip, and a plurality of second slave chips cascaded together that are all connected to the ZQ calibration resistor, where first transmission terminals and second transmission terminals are configured to transmit a ZQ flag signal; and an identification module configured to identify a priority calibration chip and a delay calibration chip, and identify the slave chip cascaded with the priority calibration chip as a primary slave chip and the slave chip cascaded with the delay calibration chip as a secondary slave chip.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, where a functional structure layer is formed on a surface of the substrate, and particles are provided on the surface of the functional structure layer; forming a first dielectric layer on the surface of the substrate, where the first dielectric layer covers the functional structure layer; grinding to remove part of the first dielectric layer until the particles are exposed, and removing the particles, to form first recesses on a surface of the remaining first dielectric layer; and forming a second dielectric layer on the surface of the first dielectric layer, where the second dielectric layer fills the first recesses.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a process recipe, a method and a system for generating same, and a semiconductor manufacturing method. The method for generating a diffraction-based process recipe includes: providing a basic process recipe, the basic process recipe is used to form an initial alignment pattern; and performing a feedback correction step for at least one time to adjust the basic process recipe and obtain an actual process recipe, which each time includes: obtaining a first pattern and a second pattern based on the basic process recipe prior to a current feedback correction step, the first pattern is the initial alignment pattern that is developed, the second pattern is the initial alignment pattern that is etched; and adjusting the basic process recipe prior to the current feedback correction step based on a difference between the first pattern and the second pattern.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a base; forming a first dielectric layer on the base; then forming a plurality of first mask patterns each having zigzag shape on the first dielectric layer, in which the first mask patterns extend in a first direction; forming a plurality of second mask patterns each having zigzag shape on the first mask patterns, in which the second mask patterns extend in a second direction different from the first direction, and projections of the first mask patterns on the first dielectric layer and projections of the second mask patterns on the first dielectric layer overlap with each other to form polygons; and etching the first dielectric layer by using the second mask patterns and the first mask patterns as masks to form openings.

Abstract: An anti-fuse cell structure includes: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and a Blow Enable (BE) line electrically connected to a first end of the first anti-fuse transistor, and configured to perform programming operation on the first anti-fuse transistor.

Abstract: A chip testing method includes: a data receiving window corresponding to each chip to be tested is determined; a time adjustment parameter corresponding to each chip to be tested is determined according to the data receiving window corresponding to each chip to be tested and a data input window preset for a test machine is determined; an actual input time point corresponding to each chip to be tested is determined according to the time adjustment parameter corresponding to each chip to be tested; and data is inputted to each chip to be tested at the actual input time point corresponding to the each chip to be tested, to enable each chip to be tested to receive the data inputted by the test machine in the data receiving window corresponding to the each chip to be tested.

Abstract: A developing method and apparatus are provided. The developing method includes: obtaining airflow conditions above a wafer to be developed; setting a developing procedure according to the airflow conditions; and developing the wafer to be developed according to the developing procedure.

Abstract: Embodiments of the present invention provide a method for manufacturing a semiconductor structure, which includes: a base is provided and a stack layer is formed on the base, wherein the stack layer includes at least a first sacrificial layer, and a material of the first sacrificial layer includes an amorphous elemental semiconductor material; second hard mask patterns are formed on the first sacrificial layer through a self-aligned process; a doping process is performed, which includes the operation that a region of the first sacrificial layer exposed from gaps between the second hard mask patterns is doped; the second hard mask patterns are removed; and an undoped region of the first sacrificial layer is removed through a selective etching process so as to form first sacrificial patterns.

Abstract: Embodiments relate to the field of semiconductor circuit design, and more particularly, to a data processing method, a data processing structure, and a memory. The data processing method includes: obtaining raw data to be stored, and grouping the raw data to obtain first split data, the first split data having equal number of code elements; encoding each of the first split data to generate first encoded data, where the first encoded data includes the first split data and check data corresponding to the first split data; reorganizing the first encoded data to generate write data; storing the write data into a memory cell; and obtaining read data in the memory cell, and decoding and checking the read data to generate corrected read data, to correct a multi-bit burst error occurring in the memory during data storage or data transmission.

Abstract: Disclosed are a semiconductor structure, a memory and a method for operating the memory. The semiconductor structure includes: a substrate; a first gate structure and a second gate structure that are located on a surface of the substrate and have a same thickness smaller than a preset thickness; and a first doped area and a second doped area that are located in the substrate and are respectively located on two sides of the first gate structure. The first gate structure forms a selection transistor with the first and second doped areas; an orthographic projection of the second gate structure on the substrate is at least partially overlapped with the second doped area. The second gate structure and the second doped area form an antifuse bit structure. A breakdown state and a non-breakdown state of the antifuse bit structure are configured to represent different stored data.

Abstract: An oscillator layout includes: a first row layout region constituted by sequentially arranging a second B layout region, second A layout region, third B layout region and third A layout region in parallel; and a second row layout region constituted by sequentially arranging a first A layout region, first B layout region, fourth A layout region and fourth B layout region in parallel. Inputs and outputs of the first A layout region, second A layout region, third A layout region and fourth A layout region constitute a first ring topology, inputs and outputs of the first B layout region and third B layout region constitute a second ring topology, inputs and outputs of the second B layout region and fourth B layout region constitute a third ring topology, the second ring topology and third ring topology are both electrically connected to the first ring topology.

Abstract: An amplification circuit includes: a sense amplification circuit including a read node, a complementary read node, a first node and a second node; an isolation circuit, which couples the read node to a bit line and couples the complementary read node to a complementary bit line in a sense amplification stage; an offset cancellation circuit, which couples the bit line to the complementary read node and couple the complementary bit line to read node in an offset cancellation stage; and a first power supply circuit, coupled to the first node, including a first power supply and a second power supply, a power supply voltage of the first power supply being higher than that of the second power supply, the first power supply circuit couples the first power supply to the first node in offset cancellation stage, and couples the second power supply to the first node in sense amplification stage.

Abstract: A voltage detection circuit including a threshold setting module and a voltage conversion module, and a voltage detection method are provided. In the threshold setting module, a first input end is configured to receive a voltage to be detected, a second input end is configured to receive a threshold regulation signal, a power supply end is connected to a first voltage and is configured to set a voltage regulation range according to the threshold regulation signal, determine a first voltage regulation value in the voltage regulation range according to the voltage to be detected, and generate a control voltage according to the first voltage and the first voltage regulation value. The voltage conversion module is configured to output a first level when the control voltage is greater than a preset value and output a second level when the control voltage is less than or equal to the preset value.

Abstract: The present disclosure provides a chemical solution preparation system and method. The chemical solution preparation system includes: a first mixing system, configured to mix a first chemical solution and a first diluent to obtain a first mixture; a second mixing system, configured to mix a second chemical solution and a second diluent to obtain a second mixture; a third mixing system, configured to mix the first mixture, the second mixture, and a third diluent to obtain a third mixture; an output system, configured to output the third mixture to a spray apparatus of the chemical mechanical polishing device; a sampling system, configured to collect a sample of the third mixture output from the output system; and a monitoring system, configured to monitor a status of the first mixture, a status of the second mixture, and a status of the third mixture.

Abstract: A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.