Abstract: A memory circuit at least includes a plurality of memory banks, where each of the memory banks includes a first memory sub-bank, a second memory sub-bank and a third memory sub-bank sequentially arranged, the second memory sub-bank including a first memory section and a second memory section, the first memory sub-bank and the second memory section being configured to store upper bytes, and the first memory section and the third memory sub-bank being configured to store lower bytes.

Abstract: A local sensing amplifier and a memory are provided. The local sensing amplifier is connected to a global signal line and is connected to a sense amplifier array by means of a local signal line and a complementary local signal line. The local sensing amplifier transmits a signal on the local signal line to the global signal line when a read control signal is received, and to transmit a signal on the global signal line to the local signal line when a write control signal is received. The local sensing amplifier includes a precharge circuit connected to a preset voltage source, the local signal line and the complementary local signal line. The preset voltage source provides a first voltage in a read-write interval and provide a second voltage in an idle period. The precharge circuit transmits first voltage to the local signal line and the complementary local signal line.

Abstract: A semiconductor structure includes: at least one ground layer and at least one power supply layer arranged in a preset direction, and a via structure extending in the preset direction; and a first protection structure and a second protection structure that are sequentially disposed around a sidewall of the via structure in a direction surrounding the sidewall of the via structure and are spaced apart from each other, where a first spacing is formed between the first protection structure and the via structure, at least partial region of the first protection structure is electrically connected with the at least one ground layer, a second spacing is formed between at least partial region of the second protection structure and the via structure, and the second protection structure is electrically connected with the at least one power supply layer.

Abstract: A semiconductor structure includes a substrate, bit line structures located on the substrate, capacitor contact holes located on each of two opposite sides of the bit line structure, and isolation side walls, each of the isolation side walls is located between a respective bit line structure and the capacitor contact holes on one side of the bit line structure. A gap isolation layer is provided between the isolation side walls located on two opposite sides of the bit line structure. The gap isolation layer is located on the bit line structure, and a first gap is provided inside the gap isolation layer. A second gap is provided between the isolation side wall and the gap isolation layer.

Abstract: A semiconductor structure and a semiconductor structure manufacturing method is provided. The semiconductor structure includes: a wordline; and a first bitline and a second bitline located on two sides of the wordline and a first storage structure and a second storage structure located on the two sides of the wordline, the first bitline and the second bitline being connected to the first storage structure and the second storage structure respectively through a transistor. An extension direction of the first bitline and an extension direction of the wordline are at an acute or obtuse angle. In this way, the first storage structure and the second storage structure are provided on both sides of the wordline, which can increase storage capacity.

Abstract: A memory test method includes: obtaining a preset memory and a memory to be tested; setting the memory to be tested as a reserved memory; starting an operating system, wherein the operating system runs in the preset memory; and executing a memory test program to test the memory to be tested, wherein the memory test program runs in the preset memory.

Abstract: Provided is data receiving circuit, data receiving system and memory device. The data receiving circuit includes: first amplification circuit, configured to receive data signal, first reference signal and second reference signal, perform first comparison on the data signal and the first reference signal in response to sampling clock signal and output first signal pair, and perform second comparison on the data signal and the second reference signal and output second signal pair; second amplification circuit, configured to receive enable signal and feedback signal, selectively receive the first signal pair or the second signal pair as input signal pair based on the feedback signal during period in which the enable signal is at first level, receive the first signal pair during period in which the enable signal is at second level, amplify voltage difference of the first signal pair, and output first output signal and second output signal.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.

Abstract: Embodiments of the disclosure provide a method for manufacturing a semiconductor device. The method includes: providing a substrate having at least one trench; forming a first polysilicon layer in the trench, covering a sidewall and a bottom of the trench and not fully fills the trench; annealing the first polysilicon layer; and forming a second polysilicon layer at a region of the trench where the first polysilicon layer is not filled after annealing.

Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes a substrate, a gate structure and a self-aligned contact structure. The substrate includes a source region and a drain region; the gate structure is formed on the substrate and are located between the source region and the drain region; and the self-aligned contact structure is formed on the substrate and includes a first contact structure, a second contact structure and a third contact structure sequentially connected in a direction perpendicular to the substrate, the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate.

Abstract: A layout of a driving circuit, a semiconductor structure and a semiconductor memory are provided. The layout includes P-type transistors, N-type transistors and four test modules. The four test modules are distributed on both sides of the P-type transistors and the N-type transistors in an upper-lower symmetrical structure, and the P-type transistors and the N-type transistors have an upper-lower structure distribution in the middle of the four test modules.

Abstract: A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: Embodiments of the present disclosure provide a control method, a semiconductor memory, and an electronic device. When the semiconductor memory is in a preset test mode, a first Model Register (MR) and a second MR related to a Data Pin (DQ) are allowed to directly define the impedance of a Data Mask Pin (DM). The DM does not need to add definition of an output driver state and a related control circuit for the preset test mode to ensure that the preset test mode is adapted to the DM. The impedance of the DM may be tested in the preset test mode to avoid circuit processing errors.

Abstract: The present disclosure provides a method of forming a semiconductor structure and a semiconductor structure. The method of forming a semiconductor structure includes: providing an initial structure, where the initial structure includes a substrate and bit line structures arranged at intervals on the substrate; forming an initial protective structure, where the initial protective structure at least covers a part of sidewalls of each of the bit line structures, and the initial protective structure has a first height in a direction parallel to the bit line structures; forming a shielding structure, where the shielding structure at least covers a part of sidewalls of the initial protective structure; and removing at least a part of the initial protective structure exposed by the shielding structure by using the shielding structure as an etching selection layer, to form protective structures each having a second height.

Abstract: The present application provides a detaching and installing device for a gas distribution plate of an etching machine, and the etching machine, and relates to the field of semiconductor manufacturing technologies, aiming at addressing the problems that it is quite difficult to detach and install the gas distribution plate of the etching machine and that the gas distribution plate is highly likely to be polluted. The detaching and installing device for the gas distribution plate of the etching machine includes a gripping member, a connecting member and a fixing member, the fixing member is detachably connected to the gas distribution plate of the etching machine, and the gripping member and the fixing member are connected through the connecting member; the gripping member is provided thereon with a gripping portion for grip by a user hand.

Abstract: The signal generator includes the following: an oscillation generation circuit, configured to generate an initial oscillation signal based on an oscillation control signal; a duty cycle correction circuit, connected to an output end of the oscillation generation circuit and configured to adjust a duty cycle of the initial oscillation signal based on a duty cycle control signal, to generate an adjusted oscillation signal; an output interface, connected to an output end of the duty cycle correction circuit and configured to output the adjusted oscillation signal to an external test system; and an amplitude adjustment circuit, connected to the output end of the duty cycle correction circuit and configured to adjust an amplitude of the adjusted oscillation signal based on an amplitude control signal, to generate a test signal.

Abstract: Disclosed are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a substrate and a dielectric layer, where the substrate includes a front surface and a back surface that are opposite to each other; the dielectric layer is formed on the front surface; the base is provided with a via hole; the via hole penetrates the substrate from the back surface of the substrate and extends to the dielectric layer; an insulating layer, located on an inner wall surface of the via hole; and a conductive structure, where the conductive structure includes a first conductive layer and a second conductive layer connected to each other; the first conductive layer is close to a bottom of the via hole, and the second conductive layer is close to a top of the via hole.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided. A lower electrode is formed on the substrate. A capacitor dielectric layer is formed on a surface of the lower electrode. The capacitor dielectric layer includes at least one zirconium oxide layer. The capacitor dielectric layer is subjected with microwave annealing treatment to convert a crystal phase of zirconium oxide to a tetragonal crystal phase. An upper electrode is formed on a surface of the capacitor dielectric layer.

Abstract: The present disclosure provides an electronic device and a driving method. The electronic device comprises: a sensitivity amplifier and a voltage adjustment circuit. The sensitivity amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The control circuit is connected to the third node, the fourth node, and a preset voltage terminal. A first control signal terminal responds to the signal of the first control signal terminal to connect the preset voltage terminal and the third node and the fourth node. The preset voltage terminal inputs a preset voltage signal. The electronic device write a preset voltage signal of a suitable size to the sensitivity amplifier through the voltage adjustment circuit, so that the sensitivity amplifier has an appropriate voltage difference between the bit line and the complementary bit line during offset elimination.