Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
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Patent number: 12317487Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a fabrication method thereof, and a memory. The semiconductor structure includes: a base substrate including a first side and a second side opposite to each other; a first device layer including a first device, the first device layer being arranged on the first side of the base substrate; and a second device layer including a second device, the second device layer being arranged on the second side of the base substrate. At least part of the first device and at least part of the second device share a first doped region.Type: GrantFiled: June 23, 2022Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Heng-Chia Chang
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Patent number: 12315554Abstract: A decoding drive circuit includes at least one decoding driver. The decoding driver includes a first-stage drive circuit and a second-stage drive circuit. Herein, the first-stage drive circuit is configured to receive an enabling control signal, a decoding input signal and a drive control signal, and generate a first drive signal and a second drive signal according to the enabling control signal, the drive control signal and the decoding input signal. The second-stage drive circuit is configured to generate a target word line drive signal according to the first drive signal and the second drive signal. Thus, the embodiments of the disclosure provide a new decoding drive circuit.Type: GrantFiled: February 8, 2023Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Weibing Shang, Xianjun Wu, Minghao Li
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Patent number: 12315799Abstract: A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.Type: GrantFiled: May 28, 2024Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xianlei Cao
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Patent number: 12315557Abstract: A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.Type: GrantFiled: February 14, 2023Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kangling Ji
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Patent number: 12317473Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes: a semiconductor substrate, where a plurality of columnar active areas are formed on the semiconductor substrate, the plurality of columnar active areas are spaced apart by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; a plurality of third trenches positioned in the semiconductor substrate at bottoms of the second trenches, where the third trenches are recessed to bottoms of the columnar active areas, and a bottom surface of a given one of the third trenches is higher than a bottom surface of the given first trench; and a plurality of metal silicide bit lines extending along the first direction in the semiconductor substrate positioned at the bottoms of the plurality of third trenches and the bottoms of the plurality of columnar active areas.Type: GrantFiled: September 22, 2022Date of Patent: May 27, 2025Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGYInventors: Guangsu Shao, Deyuan Xiao, Yunsong Qiu, Yuhan Zhu
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Patent number: 12315546Abstract: A signal control circuit includes: a generating circuit configured to accumulate execution times of an activation operation and output a block signal in response to an accumulated value being greater than or equal to a first preset value; and a logic circuit configured to receive an activation operation signal and the block signal, block outputting of the activation operation signal in response to receiving the block signal, and output the activation operation signal in response to not receiving the block signal.Type: GrantFiled: February 10, 2023Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Enpeng Gao
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Patent number: 12315596Abstract: Embodiments of the present disclosure provide a word line driver, a word line driver array, and a semiconductor structure, relating to the technical field of semiconductors. The word line driver includes: a zeroth P-channel metal oxide semiconductor (PMOS) transistor, a zeroth N-channel metal oxide semiconductor (NMOS) transistor, and a first NMOS transistor, the zeroth PMOS transistor being provided with a gate connected to a gate of the first NMOS transistor and configured to receive a first control signal, a source configured to receive a second control signal, and a drain connected to a drain of the first NMOS transistor, the zeroth NMOS transistor being provided with a gate configured to receive a second control complementary signal, and a drain of the zeroth NMOS transistor and the drain of the first NMOS transistor being configured to be connected to a word line.Type: GrantFiled: January 12, 2023Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Sungsoo Chi, Fengqin Zhang, Shuyan Jin
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Patent number: 12317483Abstract: Embodiments relate to a semiconductor structure and a method for fabricating. The semiconductor structure includes: a substrate, word lines, bit lines, and word line isolation structures. Active pillars arranged in an array are provided on a surface of the substrate, and the active pillars include channel regions, and a top doped region positioned on an upper side of the channel region and a bottom doped region positioned on a lower side of the channel region. The word lines extend along a first direction and surround the channel regions of a row of the active pillars arranged along the first direction. The bit lines extend along a second direction and are electrically connected to the bottom doped regions of a column of the active pillars arranged along the second direction, and in a direction facing away from the surface of the substrate.Type: GrantFiled: September 27, 2022Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangsu Shao, Deyuan Xiao
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Patent number: 12317484Abstract: Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a semiconductor substrate, the semiconductor substrate being provided with a plurality of first bit lines extending along a first direction; forming a first transistor array on the semiconductor substrate, the first transistor array including a plurality of first semiconductor pillars; forming first word lines, each of the plurality of first semiconductor pillars being connected to a corresponding one of the first word lines and a corresponding one of the plurality of first bit lines; forming a second transistor array on the first transistor array, the second transistor array including a plurality of second semiconductor pillars, and the plurality of first semiconductor pillars being corresponding to the plurality of second semiconductor pillars one to one; and forming second word lines and second bit lines to form a 2T0C semiconductor structure.Type: GrantFiled: August 3, 2022Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangsu Shao, Deyuan Xiao
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Patent number: 12315839Abstract: A wafer bonding device includes: a first fixing apparatus fixing a first wafer, on which a first alignment mark is disposed; a second fixing apparatus fixing a second wafer, on which a second alignment mark is disposed, the second fixing apparatus being disposed opposite to the first fixing apparatus; a reflection member between the first and second fixing apparatuses; a mark reader which reads position information about the first and second alignment marks by means of the reflection member, for aligning the first wafer with the second wafer; and a heating apparatus, configured to heat the first wafer or the second wafer to thermally expand the first wafer or the second wafer so that the first alignment mark or the second alignment mark is located at a central position of a field of view of the mark reader. A wafer bonding method also is involved.Type: GrantFiled: June 2, 2022Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Chih-Wei Chang
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Patent number: 12317470Abstract: The present disclosure provides a semiconductor device, a semiconductor structure and a formation method thereof, and relates to the field of semiconductor technologies. The formation method includes: providing a substrate, and forming a sacrificial layer on the substrate; patterning the sacrificial layer to form trenches and through holes distributed side by side in the sacrificial layer; forming insulating layers covering a sidewall of the trench and a sidewall of the through hole; sequentially forming a conductive layer and a passivation layer in the trench and the through hole to form a bitline structure in the trench; and removing the passivation layer in the through hole to form a capacitor contact structure in the through hole.Type: GrantFiled: October 28, 2021Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Ping-Heng Wu
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Patent number: 12317503Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a memory device, and a manufacturing method and a driving method thereof. The memory device includes: a substrate; a stacked structure, where the stacked structure includes a first gate layer, a second gate layer, and interlayer isolation layers, one of the interlayer isolation layers is located between the first gate layer and the second gate layer, and another one of the interlayer isolation layers is located between the first gate layer and the substrate; and a memory structure, including a through hole penetrating the stacked structure, and a trench structure filled in the through hole. The present disclosure enables the memory device to be used as nonvolatile memory with different storage modes, thereby realizing versatility of the memory device.Type: GrantFiled: April 29, 2022Date of Patent: May 27, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Shuai Guo, Mingguang Zuo, Shijie Bai
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Publication number: 20250165194Abstract: A memory circuit at least includes a plurality of memory banks, where each of the memory banks includes a first memory sub-bank, a second memory sub-bank and a third memory sub-bank sequentially arranged, the second memory sub-bank including a first memory section and a second memory section, the first memory sub-bank and the second memory section being configured to store upper bytes, and the first memory section and the third memory sub-bank being configured to store lower bytes.Type: ApplicationFiled: January 22, 2025Publication date: May 22, 2025Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: SUNGSOO CHI
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Patent number: 12302634Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a first transistor, located on the substrate; a second transistor, located above the first transistor; and a gate structure, the gate structure including a first gate layer and a second gate layer, which connected to each other, the first gate layer surrounding the first transistor and the second gate layer surrounding the second transistor; an extension direction of the first transistor and an extension direction of the second transistor are both perpendicular to the substrate.Type: GrantFiled: January 13, 2022Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Kui Zhang, Zhan Ying
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Patent number: 12300350Abstract: A receiving circuit includes: an input buffer configured to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and output a first output signal and a second output signal, where the first input signal and the second input signal are respectively a first signal and a second signal in a differential mode, the first input signal is one of the first signal and the second signal in a single-ended mode, the second input signal is a reference voltage signal, and the first signal and the second signal are complementary; and a conversion module configured to receive the first output signal and the second output signal and amplify a voltage difference between the first output signal and the second output signal.Type: GrantFiled: January 6, 2023Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Feng Lin
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Patent number: 12300744Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a semiconductor substrate, the semiconductor substrate is provided with first trenches extending along a first direction and second trenches extending along a second direction, the first trenches intersect with the second trenches to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench is filled with a first dielectric layer, a second dielectric layer is provided on a top of the semiconductor pillar, and a third dielectric layer is provided on a sidewall of the first trench; an isolation layer, located in the semiconductor substrate below the first trenches and extending along the second direction; and a bit line, located on a surface of the isolation layer and extending along the second direction, the bit line is connected to a bottom of the semiconductor pillar.Type: GrantFiled: September 26, 2022Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Deyuan Xiao, Guangsu Shao, Yunsong Qiu, Yi Jiang, Youming Liu
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Patent number: 12300308Abstract: A data transmission circuit, a data transmission method and a semiconductor memory are provided. The data transmission circuit includes a control circuit and a processing circuit. The control circuit is configured to receive a first enable signal, and control the processing circuit to be in an operating state when the first enable signal is in an active state, and control the processing circuit to be in a non-operating state when the first enable signal is in a non-active state. The processing circuit is configured to receive an initial data signal and drive the initial data signal to obtain a target transmission signal when the processing circuit is in the operating state.Type: GrantFiled: July 14, 2022Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Zhonglai Liu
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Patent number: 12300348Abstract: A circuit for signal transmission, memory, and method for signal transmission are provided. The circuit includes: a signal processing circuit, configured to receive an input first signal, obtain a second signal by processing the first signal in a preset processing manner, and take the second signal as an output signal of the signal processing circuit; and a selection circuit, configured to receive the input first signal, the second signal and a control signal, and take the first signal or the second signal as an output signal of the selection circuit according to the control signal.Type: GrantFiled: April 26, 2022Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kiho Kim
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Patent number: 12300354Abstract: Embodiments relate to the field of semiconductors and provide a wordline driver circuit and a memory. The wordline driver circuit may at least include a plurality of wordline drivers. Each of the plurality of wordline drivers includes a corresponding PMOS transistor and an NMOS transistor, the plurality of PMOS transistors included in the plurality of wordline drivers are arranged side by side, and the plurality of NMOS transistors included in the plurality of wordline drivers are arranged side by side. In an arrangement direction of the plurality of PMOS transistors, the plurality of PMOS transistors are positioned on the same sides of the plurality of NMOS transistors.Type: GrantFiled: June 22, 2022Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Guifen Yang
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Patent number: 12301237Abstract: A voltage conversion circuit and a memory are provided. The voltage conversion circuit includes a driving circuit and a receiving circuit. The driving circuit is powered by a first voltage, and outputs a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage. The receiving circuit is powered by the first voltage, receives the first signal at a first input end, and receives a sampling signal at a second input end. The receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage.Type: GrantFiled: January 20, 2023Date of Patent: May 13, 2025Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kangling Ji